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10505caae156994aa42ef9b421b70dabc82ad040
vortex/hw
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Blaise Tine 10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
2020-11-08 01:31:46 -08:00
..
configs
project directories reorganization
2020-04-14 06:35:20 -04:00
models/memory
RTL code refactoring
2020-04-19 03:38:00 -04:00
modelsim
yosys synthesis refactoring
2020-07-10 18:56:41 -04:00
old_rtl
refactoring fixes
2020-04-14 19:39:59 -04:00
opae
refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
2020-11-08 01:31:46 -08:00
rtl
refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
2020-11-08 01:31:46 -08:00
scripts
cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!
2020-11-05 03:49:50 -08:00
simulate
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
syn
minor update
2020-10-20 08:45:21 -07:00
unit_tests
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
.gitignore
adding dram writeenable support + scheduler bug fixes
2020-05-27 19:00:23 -04:00
Makefile
scope refactoring
2020-10-03 18:53:21 -04:00
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