344 lines
16 KiB
Verilog
344 lines
16 KiB
Verilog
`include "VX_define.vh"
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module Vortex_Socket (
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// Clock
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input wire clk,
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input wire reset,
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// DRAM request
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output wire dram_req_valid,
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output wire dram_req_rw,
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output wire[`VX_DRAM_BYTEEN_WIDTH-1:0] dram_req_byteen,
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output wire[`VX_DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire[`VX_DRAM_LINE_WIDTH-1:0] dram_req_data,
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output wire[`VX_DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire[`VX_DRAM_LINE_WIDTH-1:0] dram_rsp_data,
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input wire[`VX_DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Snoop request
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input wire snp_req_valid,
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input wire[`VX_DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire[`VX_SNP_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire[`VX_SNP_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// I/O request
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output wire io_req_valid,
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output wire io_req_rw,
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output wire[3:0] io_req_byteen,
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output wire[29:0] io_req_addr,
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output wire[31:0] io_req_data,
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output wire[`VX_CORE_TAG_WIDTH-1:0] io_req_tag,
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input wire io_req_ready,
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// I/O response
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input wire io_rsp_valid,
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input wire[31:0] io_rsp_data,
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input wire[`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag,
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output wire io_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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if (`NUM_CLUSTERS == 1) begin
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Vortex_Cluster #(
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.CLUSTER_ID(`L3CACHE_ID)
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) Vortex_Cluster (
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.clk (clk),
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.reset (reset),
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.dram_req_valid (dram_req_valid),
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.dram_req_rw (dram_req_rw),
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.dram_req_byteen (dram_req_byteen),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_tag (dram_req_tag),
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.dram_req_ready (dram_req_ready),
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_data (dram_rsp_data),
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.dram_rsp_tag (dram_rsp_tag),
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.dram_rsp_ready (dram_rsp_ready),
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.snp_req_valid (snp_req_valid),
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.snp_req_addr (snp_req_addr),
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.snp_req_tag (snp_req_tag),
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.snp_req_ready (snp_req_ready),
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.snp_rsp_valid (snp_rsp_valid),
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.snp_rsp_tag (snp_rsp_tag),
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.snp_rsp_ready (snp_rsp_ready),
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.io_req_valid (io_req_valid),
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.io_req_rw (io_req_rw),
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.io_req_byteen (io_req_byteen),
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.io_req_addr (io_req_addr),
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.io_req_data (io_req_data),
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.io_req_tag (io_req_tag),
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.io_req_ready (io_req_ready),
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.io_rsp_valid (io_rsp_valid),
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.io_rsp_data (io_rsp_data),
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.io_rsp_tag (io_rsp_tag),
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.io_rsp_ready (io_rsp_ready),
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.busy (busy),
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.ebreak (ebreak)
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);
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end else begin
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag;
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wire l3_core_req_ready;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
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wire[`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data;
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wire[`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
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wire[`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr;
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wire[`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag;
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wire[`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready;
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wire[`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid;
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wire[`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag;
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wire[`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready;
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`IGNORE_WARNINGS_BEGIN
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wire[`NUM_CLUSTERS-1:0] per_cluster_io_req_valid;
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wire[`NUM_CLUSTERS-1:0] per_cluster_io_req_rw;
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wire[`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen;
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wire[`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr;
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wire[`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data;
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wire[`NUM_CLUSTERS-1:0][`DCORE_TAG_WIDTH-1:0] per_cluster_io_req_tag;
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wire[`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready;
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`IGNORE_WARNINGS_END
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wire[`NUM_CLUSTERS-1:0] per_cluster_busy;
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wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak;
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genvar i;
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for (i = 0; i < `NUM_CLUSTERS; i++) begin
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Vortex_Cluster #(
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.CLUSTER_ID(i)
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) Vortex_Cluster (
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.clk (clk),
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.reset (reset),
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.dram_req_valid (per_cluster_dram_req_valid [i]),
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.dram_req_rw (per_cluster_dram_req_rw [i]),
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.dram_req_byteen (per_cluster_dram_req_byteen[i]),
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.dram_req_addr (per_cluster_dram_req_addr [i]),
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.dram_req_data (per_cluster_dram_req_data [i]),
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.dram_req_tag (per_cluster_dram_req_tag [i]),
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.dram_req_ready (l3_core_req_ready),
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.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
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.dram_rsp_data (per_cluster_dram_rsp_data [i]),
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.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
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.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
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.snp_req_valid (per_cluster_snp_req_valid [i]),
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.snp_req_addr (per_cluster_snp_req_addr [i]),
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.snp_req_tag (per_cluster_snp_req_tag [i]),
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.snp_req_ready (per_cluster_snp_req_ready [i]),
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.snp_rsp_valid (per_cluster_snp_rsp_valid [i]),
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.snp_rsp_tag (per_cluster_snp_rsp_tag [i]),
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.snp_rsp_ready (per_cluster_snp_rsp_ready [i]),
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.io_req_valid (per_cluster_io_req_valid [i]),
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.io_req_rw (per_cluster_io_req_rw [i]),
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.io_req_byteen (per_cluster_io_req_byteen [i]),
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.io_req_addr (per_cluster_io_req_addr [i]),
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.io_req_data (per_cluster_io_req_data [i]),
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.io_req_tag (per_cluster_io_req_tag [i]),
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.io_req_ready (io_req_ready),
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.io_rsp_valid (io_rsp_valid),
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.io_rsp_data (io_rsp_data),
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.io_rsp_tag (io_rsp_tag),
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.io_rsp_ready (per_cluster_io_rsp_ready [i]),
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.busy (per_cluster_busy [i]),
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.ebreak (per_cluster_ebreak [i])
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);
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end
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assign io_req_valid = per_cluster_io_req_valid[0];
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assign io_req_rw = per_cluster_io_req_rw[0];
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assign io_req_byteen = per_cluster_io_req_byteen[0];
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assign io_req_addr = per_cluster_io_req_addr[0];
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assign io_req_data = per_cluster_io_req_data[0];
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assign io_req_tag = per_cluster_io_req_tag[0];
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assign io_rsp_ready = per_cluster_io_rsp_ready[0];
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assign busy = (| per_cluster_busy);
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assign ebreak = (& per_cluster_ebreak);
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// L3 Cache ///////////////////////////////////////////////////////////
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wire[`L3NUM_REQUESTS-1:0] l3_core_req_valid;
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wire[`L3NUM_REQUESTS-1:0] l3_core_req_rw;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag;
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wire[`L3NUM_REQUESTS-1:0] l3_core_rsp_valid;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data;
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wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag;
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wire l3_core_rsp_ready;
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wire[`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid;
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wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr;
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wire[`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag;
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wire[`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready;
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wire[`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid;
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wire[`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag;
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wire[`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready;
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for (i = 0; i < `L3NUM_REQUESTS; i++) begin
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// Core Request
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assign l3_core_req_valid [i] = per_cluster_dram_req_valid [i];
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assign l3_core_req_rw [i] = per_cluster_dram_req_rw [i];
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assign l3_core_req_byteen[i] = per_cluster_dram_req_byteen[i];
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assign l3_core_req_addr [i] = per_cluster_dram_req_addr [i];
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assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i];
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assign l3_core_req_data [i] = per_cluster_dram_req_data [i];
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// Core Response
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assign per_cluster_dram_rsp_valid [i] = l3_core_rsp_valid [i] && l3_core_rsp_ready;
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assign per_cluster_dram_rsp_data [i] = l3_core_rsp_data [i];
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assign per_cluster_dram_rsp_tag [i] = l3_core_rsp_tag [i];
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// Snoop Forwarding out
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assign per_cluster_snp_req_valid [i] = l3_snp_fwdout_valid[i];
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assign per_cluster_snp_req_addr [i] = l3_snp_fwdout_addr[i];
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assign per_cluster_snp_req_tag [i] = l3_snp_fwdout_tag[i];
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assign l3_snp_fwdout_ready [i] = per_cluster_snp_req_ready[i];
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// Snoop Forwarding in
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assign l3_snp_fwdin_valid [i] = per_cluster_snp_rsp_valid [i];
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assign l3_snp_fwdin_tag [i] = per_cluster_snp_rsp_tag [i];
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assign per_cluster_snp_rsp_ready [i] = l3_snp_fwdin_ready [i];
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end
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assign l3_core_rsp_ready = (& per_cluster_dram_rsp_ready);
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VX_cache #(
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.CACHE_ID (0),
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.CACHE_SIZE (`L3CACHE_SIZE),
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.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
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.NUM_BANKS (`L3NUM_BANKS),
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.WORD_SIZE (`L3WORD_SIZE),
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.NUM_REQUESTS (`L3NUM_REQUESTS),
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.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
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.CREQ_SIZE (`L3CREQ_SIZE),
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.MRVQ_SIZE (`L3MRVQ_SIZE),
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.DFPQ_SIZE (`L3DFPQ_SIZE),
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.SNRQ_SIZE (`L3SNRQ_SIZE),
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.CWBQ_SIZE (`L3CWBQ_SIZE),
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.DWBQ_SIZE (`L3DWBQ_SIZE),
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.DFQQ_SIZE (`L3DFQQ_SIZE),
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.PRFQ_SIZE (`L3PRFQ_SIZE),
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.PRFQ_STRIDE (`L3PRFQ_STRIDE),
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.DRAM_ENABLE (1),
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.WRITE_ENABLE (1),
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.SNOOP_FORWARDING (1),
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.CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH),
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.NUM_SNP_REQUESTS (`NUM_CLUSTERS),
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.SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH),
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.SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH)
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) gpu_l3cache (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (l3_core_req_valid),
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.core_req_rw (l3_core_req_rw),
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.core_req_byteen (l3_core_req_byteen),
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.core_req_addr (l3_core_req_addr),
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.core_req_data (l3_core_req_data),
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.core_req_tag (l3_core_req_tag),
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.core_req_ready (l3_core_req_ready),
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// Core response
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.core_rsp_valid (l3_core_rsp_valid),
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.core_rsp_data (l3_core_rsp_data),
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.core_rsp_tag (l3_core_rsp_tag),
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.core_rsp_ready (l3_core_rsp_ready),
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// DRAM request
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.dram_req_valid (dram_req_valid),
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.dram_req_rw (dram_req_rw),
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.dram_req_byteen (dram_req_byteen),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_tag (dram_req_tag),
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.dram_req_ready (dram_req_ready),
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// DRAM response
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_data (dram_rsp_data),
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.dram_rsp_tag (dram_rsp_tag),
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.dram_rsp_ready (dram_rsp_ready),
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// Snoop request
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.snp_req_valid (snp_req_valid),
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.snp_req_addr (snp_req_addr),
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.snp_req_tag (snp_req_tag),
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.snp_req_ready (snp_req_ready),
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// Snoop response
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.snp_rsp_valid (snp_rsp_valid),
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.snp_rsp_tag (snp_rsp_tag),
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.snp_rsp_ready (snp_rsp_ready),
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// Snoop forwarding out
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.snp_fwdout_valid (l3_snp_fwdout_valid),
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.snp_fwdout_addr (l3_snp_fwdout_addr),
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.snp_fwdout_tag (l3_snp_fwdout_tag),
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.snp_fwdout_ready (l3_snp_fwdout_ready),
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// Snoop forwarding in
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.snp_fwdin_valid (l3_snp_fwdin_valid),
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.snp_fwdin_tag (l3_snp_fwdin_tag),
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.snp_fwdin_ready (l3_snp_fwdin_ready)
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);
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end
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`ifdef DBG_PRINT_DRAM
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always_ff @(posedge clk) begin
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if (dram_req_valid && dram_req_ready) begin
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$display("%t: DRAM req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, dram_req_rw, `DRAM_TO_BYTE_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data);
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end
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if (dram_rsp_valid && dram_rsp_ready) begin
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$display("%t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data);
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end
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end
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`endif
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endmodule |