19 lines
463 B
Verilog
19 lines
463 B
Verilog
`ifndef VX_PERF_CACHE_IF
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`define VX_PERF_CACHE_IF
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`include "VX_define.vh"
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interface VX_perf_cache_if ();
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wire [`PERF_CTR_BITS-1:0] reads;
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wire [`PERF_CTR_BITS-1:0] writes;
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wire [`PERF_CTR_BITS-1:0] read_misses;
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wire [`PERF_CTR_BITS-1:0] write_misses;
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wire [`PERF_CTR_BITS-1:0] bank_stalls;
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wire [`PERF_CTR_BITS-1:0] mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] pipe_stalls;
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wire [`PERF_CTR_BITS-1:0] crsp_stalls;
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endinterface
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`endif |