41 lines
1.1 KiB
C++
41 lines
1.1 KiB
C++
#pragma once
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#include <simobject.h>
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#include "memsim.h"
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namespace vortex {
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struct CacheConfig {
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uint8_t C; // log2 cache size
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uint8_t B; // log2 block size
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uint8_t W; // log2 word size
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uint8_t A; // log2 associativity
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uint8_t addr_width; // word address bits
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uint8_t num_banks; // number of banks
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uint8_t ports_per_bank; // number of ports per bank
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uint8_t num_inputs; // number of inputs
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bool write_through; // is write-through
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bool write_reponse; // enable write response
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uint16_t victim_size; // victim cache size
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uint16_t mshr_size; // MSHR buffer size
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uint8_t latency; // pipeline latency
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};
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class Cache : public SimObject<Cache> {
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public:
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Cache(const SimContext& ctx, const char* name, const CacheConfig& config);
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~Cache();
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void step(uint64_t cycle);
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std::vector<SlavePort<MemReq>> CoreReqPorts;
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std::vector<MasterPort<MemRsp>> CoreRspPorts;
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MasterPort<MemReq> MemReqPort;
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SlavePort<MemRsp> MemRspPort;
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private:
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class Impl;
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Impl* impl_;
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};
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} |