70 lines
1.5 KiB
Verilog
70 lines
1.5 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_prefetcher #(
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parameter PRFQ_SIZE = 64,
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parameter PRFQ_STRIDE = 2,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4
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) (
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input wire clk,
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input wire reset,
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input wire dram_req,
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input wire[31:0] dram_req_addr,
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input wire pref_pop,
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output wire pref_valid,
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output wire[31:0] pref_addr
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);
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reg[`LOG2UP(PRFQ_STRIDE):0] use_valid;
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reg[31:0] use_addr;
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wire current_valid;
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wire[31:0] current_addr;
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wire current_full;
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wire current_empty;
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assign current_valid = ~current_empty;
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wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid;
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VX_generic_queue #(
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.DATAW(32),
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.SIZE(PRFQ_SIZE)
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) pfq_queue (
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.clk (clk),
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.reset (reset),
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.push (dram_req && !current_full && !pref_pop),
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.data_i (dram_req_addr & `BASE_ADDR_MASK),
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.pop (update_use),
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.data_o(current_addr),
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.empty (current_empty),
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.full (current_full)
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);
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assign pref_valid = use_valid != 0;
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assign pref_addr = use_addr;
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always @(posedge clk) begin
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if (reset) begin
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use_valid <= 0;
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use_addr <= 0;
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end else begin
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if (update_use) begin
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use_valid <= PRFQ_STRIDE;
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use_addr <= current_addr + BANK_LINE_SIZE_BYTES;
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end else if (pref_valid && pref_pop) begin
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use_valid <= use_valid - 1;
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use_addr <= use_addr + BANK_LINE_SIZE_BYTES;
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end
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end
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end
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endmodule |