189 lines
5.4 KiB
Verilog
189 lines
5.4 KiB
Verilog
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`include "VX_define.v"
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module VX_fetch (
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input wire clk,
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input wire reset,
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input wire in_memory_delay,
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input wire in_branch_stall,
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input wire in_fwd_stall,
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input wire in_branch_stall_exe,
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input wire in_gpr_stall,
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VX_icache_response_inter icache_response,
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VX_icache_request_inter icache_request,
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output wire out_delay,
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output wire out_ebreak,
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output wire[`NW_M1:0] out_which_wspawn,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_inst_meta_inter fe_inst_meta_fd,
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VX_warp_ctl_inter VX_warp_ctl
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);
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wire in_change_mask = VX_warp_ctl.change_mask;
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wire in_wspawn = VX_warp_ctl.wspawn;
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wire[31:0] in_wspawn_pc = VX_warp_ctl.wspawn_pc;
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wire in_ebreak = VX_warp_ctl.ebreak;
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wire[`NW_M1:0] in_decode_warp_num = VX_warp_ctl.warp_num;
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wire in_freeze = out_delay || in_memory_delay;
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// wire in_thread_mask[`NT_M1:0];
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// genvar ind;
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// for (ind = 0; ind <= `NT_M1; ind = ind + 1) assign in_thread_mask[ind] = VX_warp_ctl.thread_mask[ind];
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reg stall;
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reg[31:0] out_PC;
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reg[`NW_M1:0] warp_num;
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reg[`NW_M1:0] warp_state;
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reg[`NW_M1:0] warp_count;
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// reg[31:0] num_ecalls;
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initial begin
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warp_num = 0;
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warp_state = 0;
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// num_ecalls = 0;
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warp_count = 1;
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end
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// always @(posedge clk) begin
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// if (in_ebreak) begin
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// num_ecalls <= num_ecalls + 1;
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// $display("--------> New num_ecalls = %h", num_ecalls+1);
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// end
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// end
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wire add_warp = in_wspawn && !in_ebreak && !in_gpr_stall;
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wire remove_warp = in_ebreak && !in_wspawn && !in_gpr_stall;
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wire[`NW_M1:0] new_warp_state;
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wire[`NW_M1:0] new_warp_count;
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assign new_warp_count = add_warp ? (warp_count + 1) : ((remove_warp ) ? (warp_count - 1) : (warp_count ));
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assign new_warp_state = add_warp ? (warp_state + 1) : ((remove_warp && (warp_count == 3)) ? (0 ) : ( warp_state ));
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wire[`NW_M1:0] new_warp_num ;
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assign new_warp_num = (reset || (warp_num >= warp_state) || remove_warp || add_warp) ? 0 : (warp_num + 1);
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always @(posedge clk or posedge reset) begin
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warp_num <= new_warp_num;
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warp_state <= new_warp_state;
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warp_count <= new_warp_count;
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end
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// always @(posedge clk or posedge reset) begin
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// if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
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// warp_num <= 0;
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// end else begin
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// warp_num <= warp_num + 1;
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// end
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// if (add_warp) begin
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// warp_state <= warp_state + 1;
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// warp_count <= warp_count + 1;
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// // $display("Adding a new warp %h", warp_state+1);
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// end else if (remove_warp) begin // No removing, just invalidating
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// warp_count <= warp_count - 1;
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// if (warp_count == 2) begin
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// warp_state <= 0;
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// end
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// end
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// end
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assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;
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assign stall = in_gpr_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_freeze;
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assign out_which_wspawn = (warp_state+1);
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`ifdef ONLY
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`else
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wire[`NW-1:0][31:0] warp_glob_pc;
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wire[`NW-1:0][`NT_M1:0] warp_glob_valid;
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genvar cur_warp;
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generate
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for (cur_warp = 0; cur_warp < `NW; cur_warp = cur_warp + 1)
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begin
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wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == cur_warp);
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wire warp_zero_jal = VX_jal_rsp.jal && (VX_jal_rsp.jal_warp_num == cur_warp);
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wire warp_zero_branch = VX_branch_rsp.branch_dir && (VX_branch_rsp.branch_warp_num == cur_warp);
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wire warp_zero_stall = stall || (warp_num != cur_warp);
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wire warp_zero_wspawn = (cur_warp == 0) ? 0 : (in_wspawn && ((warp_state+1) == cur_warp));
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wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc;
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wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp);
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VX_warp VX_Warp(
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.clk (clk),
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.reset (reset),
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.stall (warp_zero_stall),
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.remove (warp_zero_remove),
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.in_thread_mask(VX_warp_ctl.thread_mask),
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.in_change_mask(warp_zero_change_mask),
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.in_jal (warp_zero_jal),
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.in_jal_dest (VX_jal_rsp.jal_dest),
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.in_branch_dir (warp_zero_branch),
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.in_branch_dest(VX_branch_rsp.branch_dest),
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.in_wspawn (warp_zero_wspawn),
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.in_wspawn_pc (warp_zero_wspawn_pc),
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.out_PC (warp_glob_pc[cur_warp]),
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.out_valid (warp_glob_valid[cur_warp])
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);
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end
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endgenerate
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reg[31:0] out_PC_var;
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reg[`NT_M1:0] out_valid_var;
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always @(*) begin : help
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integer g;
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integer h;
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for (g = 0; g < `NW; g = g + 1)
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begin
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if (warp_num == g[`NW_M1:0])
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begin
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out_PC_var = warp_glob_pc[g][31:0];
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for (h = 0; h < `NT; h = h + 1) out_valid_var[h] = warp_glob_valid[g][h];
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end
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end
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end
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assign out_PC = out_PC_var;
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`endif
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assign icache_request.pc_address = out_PC;
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assign out_delay = 0;
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assign fe_inst_meta_fd.warp_num = warp_num;
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genvar index;
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for (index = 0; index <= `NT_M1; index = index + 1) assign fe_inst_meta_fd.valid[index] = out_valid_var[index];
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assign fe_inst_meta_fd.instruction = (stall) ? 32'b0 : icache_response.instruction;;
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assign fe_inst_meta_fd.inst_pc = out_PC;
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// always @(*) begin
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// $display("fetch: icache_request: %x", out_PC);
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// end
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endmodule |