196 lines
6.3 KiB
Systemverilog
196 lines
6.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_trace.vh"
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module VX_issue import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_DECL
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_pipeline_perf_if.issue perf_issue_if,
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`endif
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VX_decode_if.slave decode_if,
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VX_writeback_if.slave writeback_if [`ISSUE_WIDTH],
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VX_dispatch_if.master alu_dispatch_if [`ISSUE_WIDTH],
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VX_dispatch_if.master lsu_dispatch_if [`ISSUE_WIDTH],
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`ifdef EXT_F_ENABLE
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VX_dispatch_if.master fpu_dispatch_if [`ISSUE_WIDTH],
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`endif
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`ifdef EXT_T_ENABLE
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VX_dispatch_if.master tensor_dispatch_if [`ISSUE_WIDTH],
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`ifdef EXT_T_HOPPER
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VX_tc_rf_if.slave tensor_regfile_if,
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`endif
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`endif
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VX_dispatch_if.master sfu_dispatch_if [`ISSUE_WIDTH]
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);
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VX_ibuffer_if ibuffer_if [`ISSUE_WIDTH]();
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VX_ibuffer_if scoreboard_if [`ISSUE_WIDTH]();
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VX_operands_if operands_if [`ISSUE_WIDTH]();
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`RESET_RELAY (ibuf_reset, reset);
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`RESET_RELAY (scoreboard_reset, reset);
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`RESET_RELAY (operands_reset, reset);
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`RESET_RELAY (dispatch_reset, reset);
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VX_ibuffer #(
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.CORE_ID (CORE_ID)
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) ibuffer (
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.clk (clk),
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.reset (ibuf_reset),
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.decode_if (decode_if),
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.ibuffer_if (ibuffer_if)
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);
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VX_scoreboard #(
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.CORE_ID (CORE_ID)
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) scoreboard (
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.clk (clk),
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.reset (scoreboard_reset),
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`ifdef PERF_ENABLE
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.perf_scb_stalls(perf_issue_if.scb_stalls),
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.perf_scb_any_unit_uses(perf_issue_if.scb_any_unit_uses),
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.perf_scb_fires (perf_issue_if.scb_fires),
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.perf_scb_any_fire_cycles (perf_issue_if.scb_any_fire_cycles),
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.perf_units_uses(perf_issue_if.units_uses),
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.perf_sfu_uses (perf_issue_if.sfu_uses),
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`endif
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.writeback_if (writeback_if),
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.ibuffer_if (ibuffer_if),
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.scoreboard_if (scoreboard_if)
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);
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`ifdef GPR_DUPLICATED
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VX_operands_dup #(
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`else
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VX_operands #(
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`endif
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.CORE_ID (CORE_ID),
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.CACHE_ENABLE (0)
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) operands (
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.clk (clk),
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.reset (operands_reset),
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.writeback_if (writeback_if),
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.scoreboard_if (scoreboard_if),
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.operands_if (operands_if),
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.tensor_regfile_if (tensor_regfile_if)
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);
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VX_dispatch #(
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.CORE_ID (CORE_ID)
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) dispatch (
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.clk (clk),
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.reset (dispatch_reset),
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`ifdef PERF_ENABLE
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.perf_stalls (perf_issue_if.dispatch_stalls),
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.perf_valids (perf_issue_if.dispatch_valids),
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.perf_fires (perf_issue_if.dispatch_fires),
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.perf_any_fire_cycles (perf_issue_if.dispatch_any_fire_cycles),
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`endif
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.operands_if (operands_if),
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.alu_dispatch_if(alu_dispatch_if),
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.lsu_dispatch_if(lsu_dispatch_if),
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`ifdef EXT_F_ENABLE
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.fpu_dispatch_if(fpu_dispatch_if),
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`endif
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`ifdef EXT_T_ENABLE
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.tensor_dispatch_if(tensor_dispatch_if),
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`endif
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.sfu_dispatch_if(sfu_dispatch_if)
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);
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`ifdef DBG_SCOPE_ISSUE
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if (CORE_ID == 0) begin
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`ifdef SCOPE
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wire operands_if_fire = operands_if[0].valid && operands_if[0].ready;
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wire operands_if_not_ready = ~operands_if[0].ready;
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wire writeback_if_valid = writeback_if[0].valid;
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VX_scope_tap #(
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.SCOPE_ID (2),
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.TRIGGERW (4),
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.PROBEW (`UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS +
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1 + `NR_BITS + `XLEN + 1 + 1 + (`NUM_THREADS * 3 * `XLEN) +
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`UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1)
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) scope_tap (
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.clk(clk),
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.reset(scope_reset),
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.start(1'b0),
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.stop(1'b0),
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.triggers({
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reset,
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operands_if_fire,
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operands_if_not_ready,
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writeback_if_valid
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}),
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.probes({
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operands_if[0].data.uuid,
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operands_if[0].data.tmask,
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operands_if[0].data.ex_type,
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operands_if[0].data.op_type,
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operands_if[0].data.op_mod,
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operands_if[0].data.wb,
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operands_if[0].data.rd,
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operands_if[0].data.imm,
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operands_if[0].data.use_PC,
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operands_if[0].data.use_imm,
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operands_if[0].data.rs1_data,
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operands_if[0].data.rs2_data,
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operands_if[0].data.rs3_data,
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writeback_if[0].data.uuid,
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writeback_if[0].data.tmask,
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writeback_if[0].data.rd,
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writeback_if[0].data.data,
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writeback_if[0].data.eop
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}),
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.bus_in(scope_bus_in),
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.bus_out(scope_bus_out)
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);
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`endif
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`ifdef CHIPSCOPE
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ila_issue ila_issue_inst (
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.clk (clk),
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.probe0 ({operands_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, operands_if.PC, operands_if.tmask, operands_if.wid, operands_if.ex_type, operands_if.op_type, operands_if.ready, operands_if.valid}),
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.probe1 ({writeback_if.uuid, writeback_if.data[0], writeback_if.PC, writeback_if.tmask, writeback_if.wid, writeback_if.eop, writeback_if.valid})
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);
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`endif
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end
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`else
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`SCOPE_IO_UNUSED()
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`endif
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`ifdef PERF_ENABLE
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reg [`PERF_CTR_BITS-1:0] perf_ibf_stalls;
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wire decode_stall = decode_if.valid && ~decode_if.ready;
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always @(posedge clk) begin
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if (reset) begin
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perf_ibf_stalls <= '0;
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end else begin
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perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'(decode_stall);
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end
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end
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assign perf_issue_if.ibf_stalls = perf_ibf_stalls;
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`endif
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endmodule
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