111 lines
2.6 KiB
Verilog
111 lines
2.6 KiB
Verilog
module VX_back_end (
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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output wire out_mem_delay,
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output wire gpr_stage_delay,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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VX_wb_inter VX_writeback_inter,
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VX_warp_ctl_inter VX_warp_ctl,
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VX_dcache_response_inter VX_dcache_rsp,
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VX_dcache_request_inter VX_dcache_req
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);
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VX_wb_inter VX_writeback_temp();
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assign VX_writeback_inter.wb = VX_writeback_temp.wb;
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assign VX_writeback_inter.rd = VX_writeback_temp.rd;
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assign VX_writeback_inter.write_data = VX_writeback_temp.write_data;
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assign VX_writeback_inter.wb_valid = VX_writeback_temp.wb_valid;
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assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
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// assign VX_writeback_inter(VX_writeback_temp);
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VX_mw_wb_inter VX_mw_wb();
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VX_mem_req_inter VX_exe_mem_req();
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VX_mem_req_inter VX_mem_req();
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// LSU input + output
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VX_lsu_req_inter VX_lsu_req();
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VX_inst_mem_wb_inter VX_mem_wb();
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// Exec unit input + output
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VX_exec_unit_req_inter VX_exec_unit_req();
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VX_inst_exec_wb_inter VX_inst_exec_wb();
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// GPU unit input
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VX_gpu_inst_req_inter VX_gpu_inst_req();
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// CSR unit inputs
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VX_csr_req_inter VX_csr_req();
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VX_csr_wb_inter VX_csr_wb();
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VX_gpr_stage VX_gpr_stage(
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.VX_writeback_inter(VX_writeback_temp),
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.VX_bckE_req (VX_bckE_req),
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// New
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_lsu_req (VX_lsu_req),
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.VX_gpu_inst_req (VX_gpu_inst_req),
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.VX_csr_req (VX_csr_req),
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// End new
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.memory_delay (out_mem_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_lsu load_store_unit(
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// .clk (clk),
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.VX_lsu_req (VX_lsu_req),
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.VX_mem_wb (VX_mem_wb),
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.VX_dcache_rsp(VX_dcache_rsp),
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.VX_dcache_req(VX_dcache_req),
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.out_delay (out_mem_delay)
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);
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VX_execute_unit VX_execUnit(
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// .clk (clk),
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp)
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);
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VX_gpgpu_inst VX_gpgpu_inst(
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.VX_gpu_inst_req(VX_gpu_inst_req),
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.VX_warp_ctl (VX_warp_ctl)
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);
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VX_csr_wrapper VX_csr_wrapper(
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.VX_csr_req(VX_csr_req),
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.VX_csr_wb (VX_csr_wb)
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);
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VX_writeback VX_wb(
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.VX_mem_wb (VX_mem_wb),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_csr_wb (VX_csr_wb),
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.VX_writeback_inter(VX_writeback_temp)
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);
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endmodule |