106 lines
3.9 KiB
Verilog
106 lines
3.9 KiB
Verilog
`include "VX_define.vh"
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module VX_commit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if alu_commit_if,
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VX_commit_if lsu_commit_if,
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VX_commit_if mul_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_fp_if fpu_commit_if,
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VX_commit_if gpu_commit_if,
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// outputs
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VX_wb_if writeback_if,
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VX_perf_cntrs_if perf_cntrs_if
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);
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wire [`NUM_EXS-1:0] commited_mask;
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assign commited_mask = {((| alu_commit_if.valid) && alu_commit_if.ready),
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((| lsu_commit_if.valid) && lsu_commit_if.ready),
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((| csr_commit_if.valid) && csr_commit_if.ready),
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((| mul_commit_if.valid) && mul_commit_if.ready),
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((| fpu_commit_if.valid) && fpu_commit_if.ready),
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((| gpu_commit_if.valid) && gpu_commit_if.ready)};
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wire [`NE_BITS:0] num_commits;
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VX_countones #(
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.N(`NUM_EXS)
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) valids_counter (
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.valids(commited_mask),
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.count (num_commits)
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);
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wire has_committed = (| commited_mask);
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reg [63:0] total_cycles, total_instrs;
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always @(posedge clk) begin
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if (reset) begin
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total_cycles <= 0;
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total_instrs <= 0;
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end else begin
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total_cycles <= total_cycles + 1;
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if (has_committed) begin
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total_instrs <= total_instrs + 64'(num_commits);
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end
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end
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end
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assign perf_cntrs_if.total_cycles = total_cycles;
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assign perf_cntrs_if.total_instrs = total_instrs;
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assign gpu_commit_if.ready = 1'b1; // doesn't writeback
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VX_writeback #(
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.CORE_ID(CORE_ID)
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) writeback (
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.clk (clk),
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.reset (reset),
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.alu_commit_if (alu_commit_if),
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.lsu_commit_if (lsu_commit_if),
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.csr_commit_if (csr_commit_if),
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.mul_commit_if (mul_commit_if),
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.fpu_commit_if (fpu_commit_if),
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.writeback_if (writeback_if)
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if ((| alu_commit_if.valid) && alu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=ALU, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, alu_commit_if.warp_num, alu_commit_if.curr_PC, alu_commit_if.wb, alu_commit_if.rd, alu_commit_if.data);
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end
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if ((| lsu_commit_if.valid) && lsu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=LSU, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, lsu_commit_if.warp_num, lsu_commit_if.curr_PC, lsu_commit_if.wb, lsu_commit_if.rd, lsu_commit_if.data);
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end
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if ((| csr_commit_if.valid) && csr_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=CSR, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, csr_commit_if.warp_num, csr_commit_if.curr_PC, csr_commit_if.wb, csr_commit_if.rd, csr_commit_if.data);
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end
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if ((| mul_commit_if.valid) && mul_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=MUL, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, mul_commit_if.warp_num, mul_commit_if.curr_PC, mul_commit_if.wb, mul_commit_if.rd, mul_commit_if.data);
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end
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if ((| fpu_commit_if.valid) && fpu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=FPU, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, fpu_commit_if.warp_num, fpu_commit_if.curr_PC, fpu_commit_if.wb, fpu_commit_if.rd, fpu_commit_if.data);
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end
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if ((| gpu_commit_if.valid) && gpu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=GPU, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, gpu_commit_if.warp_num, gpu_commit_if.curr_PC, gpu_commit_if.wb, gpu_commit_if.rd, gpu_commit_if.data);
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end
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end
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`endif
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endmodule
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