Files
vortex/hw/rtl/interfaces/VX_fpu_from_csr_if.v
2020-07-24 00:00:37 -04:00

13 lines
193 B
Verilog

`ifndef VX_FPU_FROM_CSR_IF
`define VX_FPU_FROM_CSR_IF
`include "VX_define.vh"
interface VX_fpu_from_csr_if ();
wire [`NW_BITS-1:0] warp_num;
wire [`FRM_BITS-1:0] frm;
endinterface
`endif