89 lines
3.2 KiB
Verilog
89 lines
3.2 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_pipe #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_csr_req_if csr_req_if,
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VX_csr_io_req_if csr_io_req_if,
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VX_wb_if csr_wb_if,
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VX_csr_io_rsp_if csr_io_rsp_if,
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input wire notify_commit
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);
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VX_csr_req_if csr_pipe_req_if();
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VX_wb_if csr_pipe_wb_if();
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VX_csr_arb csr_arb (
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.clk (clk),
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.reset (reset),
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.csr_core_req_if (csr_req_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_req_if (csr_pipe_req_if),
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.csr_rsp_if (csr_pipe_wb_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.csr_wb_if (csr_wb_if)
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);
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wire [`CSR_ADDR_SIZE-1:0] csr_addr_s2;
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wire [31:0] csr_read_data_s2;
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wire [31:0] csr_updated_data_s2;
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wire [31:0] csr_read_data_unqual;
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wire is_csr_s2 = (| csr_pipe_wb_if.valid);
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VX_csr_data #(
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.CORE_ID(CORE_ID)
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) csr_data (
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.clk (clk),
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.reset (reset),
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.read_addr (csr_pipe_req_if.csr_addr),
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.read_data (csr_read_data_unqual),
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.write_enable (is_csr_s2),
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.write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]),
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.write_addr (csr_addr_s2),
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.warp_num (csr_pipe_req_if.warp_num),
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.notify_commit (notify_commit)
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);
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wire csr_hazard = (csr_addr_s2 == csr_pipe_req_if.csr_addr)
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&& (csr_pipe_wb_if.warp_num == csr_pipe_req_if.warp_num)
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&& is_csr_s2;
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wire [31:0] csr_read_data = csr_hazard ? csr_updated_data_s2 : csr_read_data_unqual;
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reg [31:0] csr_updated_data;
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always @(*) begin
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case (csr_pipe_req_if.csr_op)
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`CSR_RW: csr_updated_data = csr_pipe_req_if.csr_mask;
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`CSR_RS: csr_updated_data = csr_read_data | csr_pipe_req_if.csr_mask;
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`CSR_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask);
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default: csr_updated_data = 32'hdeadbeef;
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endcase
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end
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wire stall = ~csr_pipe_wb_if.ready && (| csr_pipe_wb_if.valid);
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + `WB_BITS + `CSR_ADDR_SIZE + 1 + 32 + 32)
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) csr_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({csr_pipe_req_if.valid, csr_pipe_req_if.warp_num, csr_pipe_req_if.curr_PC, csr_pipe_req_if.rd, csr_pipe_req_if.wb, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data, csr_updated_data}),
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.out ({csr_pipe_wb_if.valid, csr_pipe_wb_if.warp_num, csr_pipe_wb_if.curr_PC, csr_pipe_wb_if.rd, csr_pipe_wb_if.wb, csr_addr_s2, csr_pipe_wb_if.is_io, csr_read_data_s2, csr_updated_data_s2})
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);
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign csr_pipe_wb_if.data[i] = (csr_addr_s2 == `CSR_LTID) ? i :
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(csr_addr_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) :
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csr_read_data_s2;
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end
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assign csr_pipe_req_if.ready = ~stall;
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endmodule
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