c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
136 lines
3.7 KiB
C++
136 lines
3.7 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "mem_sim.h"
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#include <vector>
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#include <queue>
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#include <stdlib.h>
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DISABLE_WARNING_PUSH
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DISABLE_WARNING_UNUSED_PARAMETER
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#define RAMULATOR
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#include <ramulator/src/Gem5Wrapper.h>
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#include <ramulator/src/Request.h>
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#include <ramulator/src/Statistics.h>
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DISABLE_WARNING_POP
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#include "constants.h"
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#include "types.h"
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#include "debug.h"
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using namespace vortex;
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class MemSim::Impl {
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private:
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MemSim* simobject_;
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Config config_;
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PerfStats perf_stats_;
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ramulator::Gem5Wrapper* dram_;
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public:
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Impl(MemSim* simobject, const Config& config)
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: simobject_(simobject)
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, config_(config)
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{
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ramulator::Config ram_config;
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ram_config.add("standard", "DDR4");
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ram_config.add("channels", std::to_string(config.channels));
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ram_config.add("ranks", "1");
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ram_config.add("speed", "DDR4_2400R");
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ram_config.add("org", "DDR4_4Gb_x8");
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ram_config.add("mapping", "defaultmapping");
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ram_config.set_core_num(config.num_cores);
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dram_ = new ramulator::Gem5Wrapper(ram_config, MEM_BLOCK_SIZE);
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Stats::statlist.output("ramulator.ddr4.log");
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}
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~Impl() {
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dram_->finish();
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Stats::statlist.printall();
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delete dram_;
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}
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const PerfStats& perf_stats() const {
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return perf_stats_;
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}
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void dram_callback(ramulator::Request& req, uint32_t tag, uint64_t uuid) {
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if (req.type == ramulator::Request::Type::WRITE)
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return;
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MemRsp mem_rsp{tag, (uint32_t)req.coreid, uuid};
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simobject_->MemRspPort.send(mem_rsp, 1);
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DT(3, simobject_->name() << "-" << mem_rsp);
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}
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void reset() {
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perf_stats_ = PerfStats();
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}
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void tick() {
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if (MEM_CYCLE_RATIO > 0) {
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auto cycle = SimPlatform::instance().cycles();
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if ((cycle % MEM_CYCLE_RATIO) == 0)
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dram_->tick();
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} else {
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for (int i = MEM_CYCLE_RATIO; i <= 0; ++i)
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dram_->tick();
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}
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if (simobject_->MemReqPort.empty())
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return;
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auto& mem_req = simobject_->MemReqPort.front();
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ramulator::Request dram_req(
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mem_req.addr,
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mem_req.write ? ramulator::Request::Type::WRITE : ramulator::Request::Type::READ,
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std::bind(&Impl::dram_callback, this, placeholders::_1, mem_req.tag, mem_req.uuid),
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mem_req.cid
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);
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if (!dram_->send(dram_req))
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return;
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if (mem_req.write) {
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++perf_stats_.writes;
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} else {
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++perf_stats_.reads;
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}
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DT(3, simobject_->name() << "-" << mem_req);
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simobject_->MemReqPort.pop();
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}
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};
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///////////////////////////////////////////////////////////////////////////////
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MemSim::MemSim(const SimContext& ctx, const char* name, const Config& config)
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: SimObject<MemSim>(ctx, name)
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, MemReqPort(this)
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, MemRspPort(this)
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, impl_(new Impl(this, config))
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{}
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MemSim::~MemSim() {
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delete impl_;
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}
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void MemSim::reset() {
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impl_->reset();
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}
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void MemSim::tick() {
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impl_->tick();
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} |