265 lines
10 KiB
Verilog
265 lines
10 KiB
Verilog
`include "VX_define.vh"
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module VX_lsu_unit #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_lsu_unit
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input wire clk,
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input wire reset,
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// Dcache interface
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VX_cache_core_req_if dcache_req_if,
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VX_cache_core_rsp_if dcache_rsp_if,
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// inputs
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VX_lsu_req_if lsu_req_if,
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// outputs
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VX_commit_if ld_commit_if,
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VX_commit_if st_commit_if
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);
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wire req_valid;
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wire [`NUM_THREADS-1:0] req_tmask;
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wire req_rw;
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wire [`NUM_THREADS-1:0][29:0] req_addr;
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wire [`NUM_THREADS-1:0][1:0] req_offset;
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wire [`NUM_THREADS-1:0][3:0] req_byteen;
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [1:0] req_sext;
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wire [`NR_BITS-1:0] req_rd;
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wire req_wb;
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wire [`NW_BITS-1:0] req_wid;
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wire [31:0] req_pc;
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wire [`NUM_THREADS-1:0][31:0] full_address;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
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end
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reg [1:0] mem_req_sext;
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always @(*) begin
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case (lsu_req_if.byteen)
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`BYTEEN_SB: mem_req_sext = 2'h1;
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`BYTEEN_SH: mem_req_sext = 2'h2;
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default: mem_req_sext = 2'h0;
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endcase
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end
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wire [`NUM_THREADS-1:0][29:0] mem_req_addr;
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wire [`NUM_THREADS-1:0][1:0] mem_req_offset;
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wire [`NUM_THREADS-1:0][3:0] mem_req_byteen;
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wire [`NUM_THREADS-1:0][31:0] mem_req_data;
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reg [3:0] wmask;
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always @(*) begin
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case (`BYTEEN_TYPE(lsu_req_if.byteen))
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0: wmask = 4'b0001;
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1: wmask = 4'b0011;
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default: wmask = 4'b1111;
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endcase
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign mem_req_addr[i] = full_address[i][31:2];
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assign mem_req_offset[i] = full_address[i][1:0];
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assign mem_req_byteen[i] = wmask << full_address[i][1:0];
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assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0};
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end
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`IGNORE_WARNINGS_BEGIN
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wire [`NUM_THREADS-1:0][31:0] req_address;
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reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH-1:0] pending_tags;
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`IGNORE_WARNINGS_END
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wire ready_in;
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wire stall_in = ~ready_in & req_valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))),
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.RESETW (1)
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) req_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_in),
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.data_in ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.rd, lsu_req_if.wb, full_address, mem_req_sext, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data}),
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.data_out ({req_valid, req_wid, req_tmask, req_pc, req_rw, req_rd, req_wb, req_address, req_sext, req_addr, req_offset, req_byteen, req_data})
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);
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// Can accept new request?
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assign lsu_req_if.ready = ~stall_in;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [31:0] rsp_pc;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][1:0] rsp_offset;
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wire [1:0] rsp_sext;
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reg [`NUM_THREADS-1:0][31:0] rsp_data;
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reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask;
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reg [`NUM_THREADS-1:0] req_sent_mask, rsp_rem_mask_n;
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wire req_sent_all;
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wire [`DCORE_TAG_ID_BITS-1:0] mbuf_waddr, mbuf_raddr;
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wire mbuf_full;
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wire mbuf_push = (| dcache_req_if.valid) && (| dcache_req_if.ready)
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&& (0 == req_sent_mask) // first submission only
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&& (0 == req_rw); // loads only
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wire mbuf_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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wire mbuf_pop = mbuf_pop_part && (0 == rsp_rem_mask_n);
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assign mbuf_raddr = dcache_rsp_if.tag[0][`DCORE_TAG_ID_BITS-1:0];
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VX_index_buffer #(
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.DATAW (`NW_BITS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 2) + 2),
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.SIZE (`LSUQ_SIZE),
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.FASTRAM (1)
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) req_metadata (
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.clk (clk),
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.reset (reset),
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.write_addr (mbuf_waddr),
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.acquire_slot (mbuf_push),
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.read_addr (mbuf_raddr),
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.write_data ({req_wid, req_pc, req_rd, req_wb, req_offset, req_sext}),
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.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_offset, rsp_sext}),
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.release_addr (mbuf_raddr),
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.release_slot (mbuf_pop),
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.full (mbuf_full)
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);
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assign req_sent_all = ((dcache_req_if.ready | req_sent_mask) & req_tmask) == req_tmask;
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always @(posedge clk) begin
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if (reset) begin
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req_sent_mask <= 0;
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end else begin
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if (req_sent_all)
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req_sent_mask <= 0;
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else
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req_sent_mask <= req_sent_mask | (dcache_req_if.valid & dcache_req_if.ready);
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end
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end
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// need to hold the acquired tag index until the full request is submitted
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reg [`DCORE_TAG_ID_BITS-1:0] req_tag_hold;
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wire [`DCORE_TAG_ID_BITS-1:0] req_tag = (0 == req_sent_mask) ? mbuf_waddr : req_tag_hold;
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always @(posedge clk) begin
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if (mbuf_push)
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req_tag_hold <= mbuf_waddr;
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end
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assign rsp_rem_mask_n = rsp_rem_mask[mbuf_raddr] & ~dcache_rsp_if.valid;
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always @(posedge clk) begin
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if (mbuf_push) begin
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rsp_rem_mask[mbuf_waddr] <= req_tmask;
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pending_tags[mbuf_waddr] <= dcache_req_if.tag[0];
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end
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if (mbuf_pop_part) begin
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rsp_rem_mask[mbuf_raddr] <= rsp_rem_mask_n;
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end
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end
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wire req_ready_dep = (!req_rw && !mbuf_full) || (req_rw && st_commit_if.ready);
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// Core Request
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assign dcache_req_if.valid = {`NUM_THREADS{req_valid && req_ready_dep}} & req_tmask & ~req_sent_mask;
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assign dcache_req_if.rw = {`NUM_THREADS{req_rw}};
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assign dcache_req_if.byteen = req_byteen;
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assign dcache_req_if.addr = req_addr;
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assign dcache_req_if.data = req_data;
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`ifdef DBG_CACHE_REQ_INFO
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assign dcache_req_if.tag = {`NUM_THREADS{{req_pc, req_wid, req_tag}}};
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`else
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assign dcache_req_if.tag = {`NUM_THREADS{req_tag}};
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`endif
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assign ready_in = req_ready_dep && req_sent_all;
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// Core Response
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] rsp_data_shifted = dcache_rsp_if.data[i] >> {rsp_offset[i], 3'b0};
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always @(*) begin
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case (rsp_sext)
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1: rsp_data[i] = {{24{rsp_data_shifted[7]}}, rsp_data_shifted[7:0]};
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2: rsp_data[i] = {{16{rsp_data_shifted[15]}}, rsp_data_shifted[15:0]};
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default: rsp_data[i] = rsp_data_shifted;
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endcase
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end
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end
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// send store commit
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wire is_store_rsp = req_valid && req_rw && req_sent_all;
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assign st_commit_if.valid = is_store_rsp;
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assign st_commit_if.wid = req_wid;
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assign st_commit_if.tmask = req_tmask;
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assign st_commit_if.PC = req_pc;
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assign st_commit_if.rd = 0;
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assign st_commit_if.wb = 0;
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assign st_commit_if.eop = 1'b1;
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assign st_commit_if.data = 0;
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// send load commit
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wire is_load_rsp = (| dcache_rsp_if.valid);
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wire load_rsp_stall = ~ld_commit_if.ready && ld_commit_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
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.RESETW (1)
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) rsp_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!load_rsp_stall),
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.data_in ({is_load_rsp, rsp_wid, dcache_rsp_if.valid, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}),
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.data_out ({ld_commit_if.valid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data, ld_commit_if.eop})
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);
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// Can accept new cache response?
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assign dcache_rsp_if.ready = ~load_rsp_stall;
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// scope registration
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`SCOPE_ASSIGN (dcache_req_fire, dcache_req_if.valid & dcache_req_if.ready);
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`SCOPE_ASSIGN (dcache_req_wid, req_wid);
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`SCOPE_ASSIGN (dcache_req_pc, req_pc);
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`SCOPE_ASSIGN (dcache_req_addr, req_address);
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`SCOPE_ASSIGN (dcache_req_rw, req_rw);
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`SCOPE_ASSIGN (dcache_req_byteen,dcache_req_if.byteen);
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`SCOPE_ASSIGN (dcache_req_data, dcache_req_if.data);
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`SCOPE_ASSIGN (dcache_req_tag, req_tag);
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`SCOPE_ASSIGN (dcache_rsp_fire, dcache_rsp_if.valid & {`NUM_THREADS{dcache_rsp_if.ready}});
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`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
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`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
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`ifdef DBG_PRINT_CORE_DCACHE
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always @(posedge clk) begin
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if ((| dcache_req_if.valid) && (|dcache_req_if.ready)) begin
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if (dcache_req_if.rw[0])
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$display("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, data=%0h",
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$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data);
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else
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$display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, rd=%0d",
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$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, req_rd);
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end
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if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
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$display("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h",
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$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data);
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end
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if (mbuf_full) begin
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$write("%t: D$%0d queue-full:", $time, CORE_ID);
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for (integer j = 0; j < `LSUQ_SIZE; j++) begin
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$write(" tag%0d=%0h", j, pending_tags[j]);
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end
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$write("\n");
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end
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end
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`endif
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endmodule
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