abnerhexu
323ed7d7e9
- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv - Update decode, execute, and dispatch logic for new instructions - Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
265 lines
10 KiB
Systemverilog
265 lines
10 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_gpu_pkg.sv"
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module VX_commit import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if.slave alu_commit_if [`ISSUE_WIDTH],
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VX_commit_if.slave lsu_commit_if [`ISSUE_WIDTH],
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`ifdef EXT_F_ENABLE
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VX_commit_if.slave fpu_commit_if [`ISSUE_WIDTH],
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`endif
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VX_commit_if.slave sfu_commit_if [`ISSUE_WIDTH],
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`ifdef EXT_T_ENABLE
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VX_commit_if.slave tensor_commit_if [`ISSUE_WIDTH],
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`endif
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// outputs
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VX_writeback_if.master writeback_if [`ISSUE_WIDTH],
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VX_commit_csr_if.master commit_csr_if,
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VX_commit_sched_if.master commit_sched_if,
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// simulation helper signals
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value
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);
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`UNUSED_PARAM (CORE_ID)
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localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `XLEN + 1 + `NR_BITS + `NUM_THREADS * `XLEN + 1 + 1 + 1 + 1;
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localparam COMMIT_SIZEW = `CLOG2(`NUM_THREADS + 1);
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localparam COMMIT_ALL_SIZEW = COMMIT_SIZEW + `ISSUE_WIDTH - 1;
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// commit arbitration
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VX_commit_if commit_if[`ISSUE_WIDTH]();
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wire [`ISSUE_WIDTH-1:0] commit_fire;
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wire [`ISSUE_WIDTH-1:0][`NW_WIDTH-1:0] commit_wid;
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wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] commit_tmask;
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wire [`ISSUE_WIDTH-1:0] commit_eop;
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wire [`ISSUE_WIDTH-1:0][`EX_BITS-1:0] commit_sel;
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`UNUSED_VAR (commit_sel)
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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`RESET_RELAY (arb_reset, reset);
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VX_stream_arb #(
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.NUM_INPUTS (`NUM_EX_UNITS),
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.DATAW (DATAW),
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.ARBITER ("R"),
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.OUT_REG (1)
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) commit_arb (
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.clk (clk),
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.reset (arb_reset),
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.valid_in ({
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sfu_commit_if[i].valid,
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`ifdef EXT_F_ENABLE
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fpu_commit_if[i].valid,
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`endif
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`ifdef EXT_T_ENABLE
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tensor_commit_if[i].valid,
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`endif
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alu_commit_if[i].valid,
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lsu_commit_if[i].valid
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}),
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.ready_in ({
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sfu_commit_if[i].ready,
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`ifdef EXT_F_ENABLE
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fpu_commit_if[i].ready,
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`endif
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`ifdef EXT_T_ENABLE
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tensor_commit_if[i].ready,
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`endif
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alu_commit_if[i].ready,
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lsu_commit_if[i].ready
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}),
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.data_in ({
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sfu_commit_if[i].data,
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`ifdef EXT_F_ENABLE
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fpu_commit_if[i].data,
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`endif
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`ifdef EXT_T_ENABLE
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tensor_commit_if[i].data,
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`endif
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alu_commit_if[i].data,
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lsu_commit_if[i].data
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}),
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.data_out (commit_if[i].data),
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.valid_out (commit_if[i].valid),
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.ready_out (commit_if[i].ready),
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.sel_out (commit_sel[i])
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);
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assign commit_fire[i] = commit_if[i].valid && commit_if[i].ready;
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assign commit_tmask[i]= {`NUM_THREADS{commit_fire[i]}} & commit_if[i].data.tmask;
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assign commit_wid[i] = commit_if[i].data.wid;
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assign commit_eop[i] = commit_if[i].data.eop;
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end
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// CSRs update
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wire [`ISSUE_WIDTH-1:0][COMMIT_SIZEW-1:0] commit_size, commit_size_r;
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wire [COMMIT_ALL_SIZEW-1:0] commit_size_all_r, commit_size_all_rr;
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wire commit_fire_any, commit_fire_any_r, commit_fire_any_rr;
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assign commit_fire_any = (| commit_fire);
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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wire [COMMIT_SIZEW-1:0] count;
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`POP_COUNT(count, commit_tmask[i]);
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assign commit_size[i] = count;
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end
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VX_pipe_register #(
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.DATAW (1 + `ISSUE_WIDTH * COMMIT_SIZEW),
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.RESETW (1)
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) commit_size_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({commit_fire_any, commit_size}),
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.data_out ({commit_fire_any_r, commit_size_r})
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);
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VX_reduce #(
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.DATAW_IN (COMMIT_SIZEW),
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.DATAW_OUT (COMMIT_ALL_SIZEW),
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.N (`ISSUE_WIDTH),
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.OP ("+")
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) commit_size_reduce (
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.data_in (commit_size_r),
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.data_out (commit_size_all_r)
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);
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VX_pipe_register #(
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.DATAW (1 + COMMIT_ALL_SIZEW),
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.RESETW (1)
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) commit_size_reg2 (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({commit_fire_any_r, commit_size_all_r}),
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.data_out ({commit_fire_any_rr, commit_size_all_rr})
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);
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reg [`PERF_CTR_BITS-1:0] instret;
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always @(posedge clk) begin
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if (reset) begin
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instret <= '0;
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end else begin
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if (commit_fire_any_rr) begin
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instret <= instret + `PERF_CTR_BITS'(commit_size_all_rr);
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end
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end
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end
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assign commit_csr_if.instret = instret;
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// Committed instructions
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// prevent underflow of the VX_pending_instr buffer
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// probably want to change this at some point
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// (i.e. pass a "don't count this towards pending instructions" signal down the pipeline)
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wire [`ISSUE_WIDTH-1:0] final_hmma;
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// if this is a "ghost" commit generated at the tensor core, don't count
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// toward committed
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wire [`ISSUE_WIDTH-1:0] tensor_ghost;
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`ifdef EXT_T_ENABLE
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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// if PC is 0, this means it is not final step of a wmma, shouldn't be committed
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assign final_hmma[i] = (commit_if[i].data.PC != 32'b0);
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// handle 'x' with ===. FIXME fix unitialization
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assign tensor_ghost[i] = (commit_if[i].data.tensor == 1'b1);
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end
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`else
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assign final_hmma = '1;
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assign tensor_ghost = '0;
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`endif
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wire [`ISSUE_WIDTH-1:0] committed = (commit_fire & commit_eop) & final_hmma & (~tensor_ghost);
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VX_pipe_register #(
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.DATAW (`ISSUE_WIDTH * (1 + `NW_WIDTH)),
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.RESETW (`ISSUE_WIDTH)
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) committed_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({committed, commit_wid}),
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.data_out ({commit_sched_if.committed, commit_sched_if.committed_wid})
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);
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// Writeback
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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assign writeback_if[i].valid = commit_if[i].valid && (commit_if[i].data.wb || commit_if[i].data.tensor);
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assign writeback_if[i].data.uuid = commit_if[i].data.uuid;
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assign writeback_if[i].data.wis = wid_to_wis(commit_if[i].data.wid);
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assign writeback_if[i].data.PC = commit_if[i].data.PC;
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assign writeback_if[i].data.tmask= commit_if[i].data.tmask;
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assign writeback_if[i].data.rd = commit_if[i].data.rd;
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assign writeback_if[i].data.data = commit_if[i].data.data;
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assign writeback_if[i].data.tensor = commit_if[i].data.tensor;
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assign writeback_if[i].data.sop = commit_if[i].data.sop;
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assign writeback_if[i].data.eop = commit_if[i].data.eop;
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assign commit_if[i].ready = 1'b1; // writeback has no backpressure
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end
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// simulation helper signal to get RISC-V tests Pass/Fail status
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reg [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value_r;
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always @(posedge clk) begin
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if (writeback_if[0].valid && !writeback_if[0].data.tensor) begin
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sim_wb_value_r[writeback_if[0].data.rd] <= writeback_if[0].data.data[0];
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end
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end
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assign sim_wb_value = sim_wb_value_r;
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`ifdef DBG_TRACE_CORE_PIPELINE_VCS
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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always @(posedge clk) begin
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if (!reset && ($time > `TRACE_STARTTIME)) begin
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if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin
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`TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop));
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`TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS);
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`TRACE(1, (" (#%0d)\n", alu_commit_if[i].data.uuid));
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end
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if (lsu_commit_if[i].valid && lsu_commit_if[i].ready) begin
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`TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, lsu_commit_if[i].data.wid, lsu_commit_if[i].data.PC, lsu_commit_if[i].data.tmask, lsu_commit_if[i].data.wb, lsu_commit_if[i].data.rd, lsu_commit_if[i].data.sop, lsu_commit_if[i].data.eop));
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`TRACE_ARRAY1D(1, lsu_commit_if[i].data.data, `NUM_THREADS);
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`TRACE(1, (" (#%0d)\n", lsu_commit_if[i].data.uuid));
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end
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`ifdef EXT_F_ENABLE
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if (fpu_commit_if[i].valid && fpu_commit_if[i].ready) begin
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`TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, fpu_commit_if[i].data.wid, fpu_commit_if[i].data.PC, fpu_commit_if[i].data.tmask, fpu_commit_if[i].data.wb, fpu_commit_if[i].data.rd, fpu_commit_if[i].data.sop, fpu_commit_if[i].data.eop));
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`TRACE_ARRAY1D(1, fpu_commit_if[i].data.data, `NUM_THREADS);
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`TRACE(1, (" (#%0d)\n", fpu_commit_if[i].data.uuid));
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end
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`endif
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if (sfu_commit_if[i].valid && sfu_commit_if[i].ready) begin
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`TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=SFU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, sfu_commit_if[i].data.wid, sfu_commit_if[i].data.PC, sfu_commit_if[i].data.tmask, sfu_commit_if[i].data.wb, sfu_commit_if[i].data.rd, sfu_commit_if[i].data.sop, sfu_commit_if[i].data.eop));
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`TRACE_ARRAY1D(1, sfu_commit_if[i].data.data, `NUM_THREADS);
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`TRACE(1, (" (#%0d)\n", sfu_commit_if[i].data.uuid));
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end
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end
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end
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end
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`endif
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endmodule
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