abnerhexu
323ed7d7e9
- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv - Update decode, execute, and dispatch logic for new instructions - Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
190 lines
5.7 KiB
Systemverilog
190 lines
5.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_execute import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter TENSOR_FP16 = 0
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) (
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`SCOPE_IO_DECL
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input wire clk,
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input wire reset,
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input base_dcrs_t base_dcrs,
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input wire downstream_mem_busy,
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// Dcache interface
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VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS],
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// commit interface
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VX_commit_csr_if.slave commit_csr_if,
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// fetch interface
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VX_sched_csr_if.slave sched_csr_if,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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VX_pipeline_perf_if.slave pipeline_perf_if,
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`endif
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`ifdef EXT_F_ENABLE
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VX_dispatch_if.slave fpu_dispatch_if [`ISSUE_WIDTH],
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VX_commit_if.master fpu_commit_if [`ISSUE_WIDTH],
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`endif
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VX_dispatch_if.slave alu_dispatch_if [`ISSUE_WIDTH],
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VX_commit_if.master alu_commit_if [`ISSUE_WIDTH],
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VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS],
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VX_dispatch_if.slave lsu_dispatch_if [`ISSUE_WIDTH],
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VX_commit_if.master lsu_commit_if [`ISSUE_WIDTH],
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VX_dispatch_if.slave sfu_dispatch_if [`ISSUE_WIDTH],
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VX_commit_if.master sfu_commit_if [`ISSUE_WIDTH],
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VX_warp_ctl_if.master warp_ctl_if,
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`ifdef EXT_T_ENABLE
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VX_dispatch_if.slave tensor_dispatch_if [`ISSUE_WIDTH],
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VX_commit_if.master tensor_commit_if [`ISSUE_WIDTH],
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`ifdef EXT_T_ASYNC
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VX_tc_rf_if.master tensor_regfile_if,
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VX_tc_bus_if.master tensor_smem_A_if,
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output logic tensor_tmem_C_wen,
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output logic tensor_tmem_C_ren,
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output logic [8:0] tensor_tmem_C_waddr,
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output logic [8:0] tensor_tmem_C_raddr,
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output logic [`NUM_THREADS*`XLEN-1:0] tensor_tmem_C_wdata,
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output logic [`NUM_THREADS*`XLEN/8-1:0] tensor_tmem_C_mask,
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input logic [`NUM_THREADS*`XLEN-1:0] tensor_tmem_C_rdata,
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VX_tc_bus_if.master tensor_smem_B_if,
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`endif
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`endif
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// simulation helper signals
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output wire sim_ebreak,
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input wire [31:0] acc_read_in,
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output wire [31:0] acc_write_out,
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output wire acc_write_en
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);
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`ifdef EXT_F_ENABLE
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VX_fpu_to_csr_if fpu_to_csr_if[`NUM_FPU_BLOCKS]();
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`endif
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`RESET_RELAY (alu_reset, reset);
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`RESET_RELAY (lsu_reset, reset);
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`RESET_RELAY (sfu_reset, reset);
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VX_alu_unit #(
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.CORE_ID (CORE_ID)
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) alu_unit (
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.clk (clk),
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.reset (alu_reset),
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.dispatch_if (alu_dispatch_if),
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.branch_ctl_if (branch_ctl_if),
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.commit_if (alu_commit_if)
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);
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`SCOPE_IO_SWITCH (1)
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VX_lsu_unit #(
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.CORE_ID (CORE_ID)
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) lsu_unit (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (lsu_reset),
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.downstream_mem_busy (downstream_mem_busy),
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.cache_bus_if (dcache_bus_if),
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.dispatch_if (lsu_dispatch_if),
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.commit_if (lsu_commit_if)
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);
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`ifdef EXT_F_ENABLE
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`RESET_RELAY (fpu_reset, reset);
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VX_fpu_unit #(
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.CORE_ID (CORE_ID)
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) fpu_unit (
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.clk (clk),
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.reset (fpu_reset),
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.dispatch_if (fpu_dispatch_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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.commit_if (fpu_commit_if)
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);
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`endif
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VX_sfu_unit #(
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.CORE_ID (CORE_ID)
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) sfu_unit (
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.clk (clk),
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.reset (sfu_reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_if),
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.pipeline_perf_if (pipeline_perf_if),
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`endif
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.base_dcrs (base_dcrs),
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.dispatch_if (sfu_dispatch_if),
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`ifdef EXT_F_ENABLE
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.fpu_to_csr_if (fpu_to_csr_if),
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`endif
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.commit_csr_if (commit_csr_if),
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.sched_csr_if (sched_csr_if),
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.warp_ctl_if (warp_ctl_if),
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.commit_if (sfu_commit_if),
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.acc_read_in (acc_read_in),
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.acc_write_out (acc_write_out),
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.acc_write_en (acc_write_en)
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);
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`ifdef EXT_T_ENABLE
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VX_tensor_core #(
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.FP16 (TENSOR_FP16)
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) tensor_core (
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.clk(clk),
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.reset(reset),
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.dispatch_if(tensor_dispatch_if),
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`ifdef EXT_T_ASYNC
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.regfile_if(tensor_regfile_if),
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.smem_A_if(tensor_smem_A_if),
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.tmem_C_wen(tensor_tmem_C_wen),
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.tmem_C_ren(tensor_tmem_C_ren),
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.tmem_C_waddr(tensor_tmem_C_waddr),
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.tmem_C_raddr(tensor_tmem_C_raddr),
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.tmem_C_wdata(tensor_tmem_C_wdata),
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.tmem_C_mask(tensor_tmem_C_mask),
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.tmem_C_rdata(tensor_tmem_C_rdata),
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.smem_B_if(tensor_smem_B_if),
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`endif
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.commit_if(tensor_commit_if)
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);
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`endif
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// simulation helper signal to get RISC-V tests Pass/Fail status
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assign sim_ebreak = alu_dispatch_if[0].valid && alu_dispatch_if[0].ready
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&& alu_dispatch_if[0].data.wis == 0
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&& `INST_ALU_IS_BR(alu_dispatch_if[0].data.op_mod)
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&& (`INST_BR_BITS'(alu_dispatch_if[0].data.op_type) == `INST_BR_EBREAK
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|| `INST_BR_BITS'(alu_dispatch_if[0].data.op_type) == `INST_BR_ECALL);
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endmodule
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