abnerhexu
323ed7d7e9
- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv - Update decode, execute, and dispatch logic for new instructions - Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
108 lines
3.9 KiB
Systemverilog
108 lines
3.9 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_trace.vh"
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module VX_ibuffer import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_decode_if.slave decode_if,
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// outputs
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VX_ibuffer_if.master ibuffer_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam ISW_WIDTH = `LOG2UP(`ISSUE_WIDTH);
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4);
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wire [`ISSUE_WIDTH-1:0] ibuf_ready_in;
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wire [ISW_WIDTH-1:0] decode_isw = wid_to_isw(decode_if.data.wid);
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wire [ISSUE_WIS_W-1:0] decode_wis = wid_to_wis(decode_if.data.wid);
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assign decode_if.ready = ibuf_ready_in[decode_isw];
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`ifdef SIMULATION
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`ifdef DBG_TRACE_CORE_PIPELINE_VCS
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wire decode_probe_pc = (decode_if.data.PC >= 32'h80000240) && (decode_if.data.PC <= 32'h80000260);
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always @(posedge clk) begin
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if (!reset && (CORE_ID == 0) && ($time > `TRACE_STARTTIME) && decode_if.valid && decode_probe_pc) begin
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`TRACE(2, ("%d: core%0d-ibuffer-probe: wid=%0d, PC=0x%0h, valid=%b, ready=%b, isw=%0d, ibuf_ready=%b, tmask=%b, ex=0x%0h, op=0x%0h (#%0d)\n",
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$time, CORE_ID, decode_if.data.wid, decode_if.data.PC, decode_if.valid, decode_if.ready,
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decode_isw, ibuf_ready_in, decode_if.data.tmask, decode_if.data.ex_type, decode_if.data.op_type,
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decode_if.data.uuid));
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end
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end
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`endif
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`endif
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VX_ibuffer_if uop_sequencer_if [`ISSUE_WIDTH]();
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`IBUF_SIZE),
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.OUT_REG (1)
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) instr_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (decode_if.valid && decode_isw == i),
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.ready_in (ibuf_ready_in[i]),
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.data_in ({
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decode_if.data.uuid,
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decode_wis,
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decode_if.data.tmask,
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decode_if.data.ex_type,
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decode_if.data.op_type,
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decode_if.data.op_mod,
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decode_if.data.wb,
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decode_if.data.use_PC,
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decode_if.data.use_imm,
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decode_if.data.PC,
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decode_if.data.imm,
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decode_if.data.rd,
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decode_if.data.rs1,
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decode_if.data.rs2,
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decode_if.data.rs3}),
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.data_out (uop_sequencer_if[i].data),
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.valid_out (uop_sequencer_if[i].valid),
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.ready_out (uop_sequencer_if[i].ready)
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);
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`ifndef L1_ENABLE
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assign decode_if.ibuf_pop[i] = uop_sequencer_if[i].valid && uop_sequencer_if[i].ready;
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`endif
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// tensor-core operation is controlled by a single macro-instruction at
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// the ISA; internally, the uop_sequencer blitzs micro-ops (counterpart
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// to Volta SASS set/step instructions) into the ibuffer upon encountering
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// this macro-instruction. this becomes a pass-through for non-tensorcore
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// instructions.
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VX_uop_sequencer uop_sequencer (
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.clk(clk),
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.reset(reset),
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.uop_sequencer_if(uop_sequencer_if[i]),
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.ibuffer_if(ibuffer_if[i])
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);
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end
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endmodule
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