139 lines
5.1 KiB
Verilog
139 lines
5.1 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_data_access #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 0,
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// Enable dram update
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parameter DRAM_ENABLE = 0,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc,
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input wire[`NR_BITS-1:0] debug_rd,
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input wire[`NW_BITS-1:0] debug_wid,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid,
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`IGNORE_WARNINGS_END
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`endif
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input wire stall,
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// Inputs
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input wire valid_in,
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] addr_in,
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`IGNORE_WARNINGS_END
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input wire writeen_in,
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input wire is_fill_in,
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input wire[`WORD_WIDTH-1:0] writeword_in,
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input wire[`BANK_LINE_WIDTH-1:0] writedata_in,
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input wire[WORD_SIZE-1:0] byteen_in,
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input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_in,
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// Outputs
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output wire[`WORD_WIDTH-1:0] readword_out,
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output wire[`BANK_LINE_WIDTH-1:0] readdata_out,
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output wire[BANK_LINE_SIZE-1:0] dirtyb_out
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);
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wire[BANK_LINE_SIZE-1:0] qual_read_dirtyb_out;
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wire[`BANK_LINE_WIDTH-1:0] qual_read_data;
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wire[BANK_LINE_SIZE-1:0] use_read_dirtyb_out;
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wire[`BANK_LINE_WIDTH-1:0] use_read_data;
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wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_byte_enable;
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wire[`BANK_LINE_WIDTH-1:0] use_write_data;
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wire use_write_enable;
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wire[`LINE_SELECT_BITS-1:0] addrline = addr_in[`LINE_SELECT_BITS-1:0];
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VX_data_store #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE)
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) data_store (
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.clk (clk),
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.reset (reset),
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.read_addr (addrline),
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.read_dirtyb (qual_read_dirtyb_out),
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.read_data (qual_read_data),
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.write_enable(use_write_enable),
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.write_fill (is_fill_in),
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.byte_enable (use_byte_enable),
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.write_addr (addrline),
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.write_data (use_write_data)
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);
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assign use_read_dirtyb_out = qual_read_dirtyb_out;
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assign use_read_data = qual_read_data;
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if (`WORD_SELECT_WIDTH != 0) begin
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wire [`WORD_WIDTH-1:0] readword = use_read_data[wordsel_in * `WORD_WIDTH +: `WORD_WIDTH];
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for (genvar i = 0; i < WORD_SIZE; i++) begin
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assign readword_out[i * 8 +: 8] = readword[i * 8 +: 8] & {8{byteen_in[i]}};
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end
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end else begin
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for (genvar i = 0; i < WORD_SIZE; i++) begin
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assign readword_out[i * 8 +: 8] = use_read_data[i * 8 +: 8] & {8{byteen_in[i]}};
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end
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end
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wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable;
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wire [`BANK_LINE_WIDTH-1:0] data_write;
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for (genvar i = 0; i < `BANK_LINE_WORDS; i++) begin
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wire word_sel = ((`WORD_SELECT_WIDTH == 0) || (wordsel_in == `UP(`WORD_SELECT_WIDTH)'(i)));
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assign byte_enable[i] = is_fill_in ? {WORD_SIZE{1'b1}} :
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word_sel ? byteen_in :
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{WORD_SIZE{1'b0}};
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assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = is_fill_in ? writedata_in[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_in;
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end
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assign use_write_enable = valid_in && writeen_in && !stall;
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assign use_byte_enable = byte_enable;
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assign use_write_data = data_write;
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assign dirtyb_out = use_read_dirtyb_out;
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assign readdata_out = use_read_data;
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`ifdef DBG_PRINT_CACHE_DATA
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always @(posedge clk) begin
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if (valid_in && !stall) begin
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if (use_write_enable) begin
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if (is_fill_in) begin
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$display("%t: cache%0d:%0d data-fill: addr=%0h, dirty=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), dirtyb_out, addrline, use_write_data);
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end else begin
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, dirty=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, byte_enable, dirtyb_out, addrline, wordsel_in, writeword_in);
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end
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end else begin
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$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), debug_wid, debug_pc, dirtyb_out, addrline, wordsel_in, qual_read_data);
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end
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end
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end
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`endif
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endmodule |