67 lines
2.5 KiB
Verilog
67 lines
2.5 KiB
Verilog
`include "VX_cache_config.v"
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module VX_cache_dram_req_arb (
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input wire clk,
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input wire reset,
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// Fill Request
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output wire dfqq_full,
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input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req,
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input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
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// DFQ Request
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output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
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input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req,
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input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
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input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
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// real Dram request
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data
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);
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wire dfqq_req;
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wire[31:0] dfqq_req_addr;
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wire dfqq_empty;
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wire dwb_valid;
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wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop
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wire dfqq_push = (|per_bank_dram_fill_req);
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VX_cache_dfq_queue VX_cache_dfq_queue(
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.clk (clk),
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.reset (reset),
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.dfqq_push (dfqq_push),
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.per_bank_dram_fill_req (per_bank_dram_fill_req),
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.per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr),
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.dfqq_pop (dfqq_pop),
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.dfqq_req (dfqq_req),
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.dfqq_req_addr (dfqq_req_addr),
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.dfqq_empty (dfqq_empty),
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.dfqq_full (dfqq_full)
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);
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wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
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VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
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.valids(per_bank_dram_wb_req),
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.index (dwb_bank),
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.found (dwb_valid)
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);
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assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & (~(1 << dwb_bank));
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assign dram_req = dwb_valid || dfqq_req;
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assign dram_req_write = dwb_valid;
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assign dram_req_read = dfqq_req && !dwb_valid;
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assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
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assign dram_req_size = `BANK_LINE_SIZE_BYTES;
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assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
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endmodule |