d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
88 lines
2.6 KiB
Systemverilog
88 lines
2.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_allocator #(
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parameter SIZE = 1,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire reset,
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input wire acquire_en,
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output wire [ADDRW-1:0] acquire_addr,
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input wire release_en,
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input wire [ADDRW-1:0] release_addr,
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output wire empty,
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output wire full
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);
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reg [SIZE-1:0] free_slots, free_slots_n;
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reg [ADDRW-1:0] acquire_addr_r;
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reg empty_r, full_r;
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wire [ADDRW-1:0] free_index;
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wire free_valid;
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always @(*) begin
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free_slots_n = free_slots;
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if (release_en) begin
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free_slots_n[release_addr] = 1;
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end
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if (acquire_en) begin
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free_slots_n[acquire_addr_r] = 0;
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end
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end
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VX_lzc #(
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.N (SIZE),
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.REVERSE (1)
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) free_slots_sel (
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.data_in (free_slots_n),
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.data_out (free_index),
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.valid_out (free_valid)
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);
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always @(posedge clk) begin
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if (reset) begin
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acquire_addr_r <= ADDRW'(1'b0);
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free_slots <= {SIZE{1'b1}};
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empty_r <= 1'b1;
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full_r <= 1'b0;
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end else begin
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if (release_en) begin
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`ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid addr %d", $time, release_addr));
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end
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if (acquire_en) begin
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`ASSERT(~full_r, ("%t: allocator is full", $time));
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end
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if (acquire_en || (release_en && full_r)) begin
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acquire_addr_r <= free_index;
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end
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free_slots <= free_slots_n;
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empty_r <= (& free_slots_n);
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full_r <= ~free_valid;
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end
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end
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assign acquire_addr = acquire_addr_r;
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assign empty = empty_r;
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assign full = full_r;
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endmodule
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`TRACING_ON
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