d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
125 lines
3.3 KiB
Systemverilog
125 lines
3.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_elastic_buffer #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter OUT_REG = 0,
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parameter LUTRAM = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (SIZE == 0) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign valid_out = valid_in;
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assign data_out = data_in;
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assign ready_in = ready_out;
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end else if (SIZE == 1) begin
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wire stall = valid_out && ~ready_out;
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VX_pipe_register #(
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.DATAW (1 + DATAW),
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.RESETW (1)
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) pipe_register (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in, data_in}),
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.data_out ({valid_out, data_out})
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);
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assign ready_in = ~stall;
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end else if (SIZE == 2) begin
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VX_skid_buffer #(
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.DATAW (DATAW),
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.OUT_REG (OUT_REG)
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) skid_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.data_out (data_out),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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end else begin
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wire empty, full;
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wire [DATAW-1:0] data_out_t;
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wire ready_out_t;
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wire push = valid_in && ready_in;
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wire pop = ~empty && ready_out_t;
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VX_fifo_queue #(
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.DATAW (DATAW),
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.DEPTH (SIZE),
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.OUT_REG (OUT_REG == 1),
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.LUTRAM (LUTRAM)
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) fifo_queue (
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.clk (clk),
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.reset (reset),
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.push (push),
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.pop (pop),
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.data_in(data_in),
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.data_out(data_out_t),
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.empty (empty),
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.full (full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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assign ready_in = ~full;
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (OUT_REG == 2)
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (~empty),
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.ready_in (ready_out_t),
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.data_in (data_out_t),
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.data_out (data_out),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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end
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endmodule
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`TRACING_ON
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