d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
73 lines
2.1 KiB
Systemverilog
73 lines
2.1 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_reduce #(
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parameter DATAW_IN = 1,
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parameter DATAW_OUT = DATAW_IN,
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parameter N = 1,
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parameter `STRING OP = "+"
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) (
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input wire [N-1:0][DATAW_IN-1:0] data_in,
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output wire [DATAW_OUT-1:0] data_out
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);
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if (N == 1) begin
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assign data_out = DATAW_OUT'(data_in[0]);
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end else begin
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localparam int N_A = N / 2;
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localparam int N_B = N - N_A;
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wire [N_A-1:0][DATAW_IN-1:0] in_A;
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wire [N_B-1:0][DATAW_IN-1:0] in_B;
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wire [DATAW_OUT-1:0] out_A, out_B;
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for (genvar i = 0; i < N_A; i++) begin
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assign in_A[i] = data_in[i];
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end
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for (genvar i = 0; i < N_B; i++) begin
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assign in_B[i] = data_in[N_A + i];
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end
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VX_reduce #(
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.DATAW_IN (DATAW_IN),
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.DATAW_OUT (DATAW_OUT),
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.N (N_A),
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.OP (OP)
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) reduce_A (
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.data_in (in_A),
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.data_out (out_A)
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);
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VX_reduce #(
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.DATAW_IN (DATAW_IN),
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.DATAW_OUT (DATAW_OUT),
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.N (N_B),
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.OP (OP)
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) reduce_B (
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.data_in (in_B),
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.data_out (out_B)
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);
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if (OP == "+") assign data_out = out_A + out_B;
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else if (OP == "^") assign data_out = out_A ^ out_B;
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else if (OP == "&") assign data_out = out_A & out_B;
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else if (OP == "|") assign data_out = out_A | out_B;
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else `ERROR(("invalid parameter"));
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end
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endmodule
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`TRACING_ON
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