41 lines
935 B
Systemverilog
41 lines
935 B
Systemverilog
`ifndef VX_PERF_CACHE_IF
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`define VX_PERF_CACHE_IF
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`include "VX_define.vh"
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interface VX_perf_cache_if ();
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wire [`PERF_CTR_BITS-1:0] reads;
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wire [`PERF_CTR_BITS-1:0] writes;
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wire [`PERF_CTR_BITS-1:0] read_misses;
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wire [`PERF_CTR_BITS-1:0] write_misses;
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wire [`PERF_CTR_BITS-1:0] bank_stalls;
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wire [`PERF_CTR_BITS-1:0] mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_stalls;
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wire [`PERF_CTR_BITS-1:0] crsp_stalls;
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modport master (
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output reads,
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output writes,
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output read_misses,
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output write_misses,
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output bank_stalls,
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output mshr_stalls,
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output mem_stalls,
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output crsp_stalls
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);
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modport slave (
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input reads,
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input writes,
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input read_misses,
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input write_misses,
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input bank_stalls,
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input mshr_stalls,
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input mem_stalls,
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input crsp_stalls
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);
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endinterface
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`endif |