c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
105 lines
4.4 KiB
Tcl
105 lines
4.4 KiB
Tcl
# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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load_package report
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set ProjectName [lindex $argv 0]
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set SynMode [lindex $argv 1]
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proc panel_to_csv { panel_name csv_file } {
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set fh [open $csv_file w]
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# Its possible for some panels to not exist based on design (ex. if no RAMs )
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set num_rows [get_number_of_rows -name $panel_name]
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catch {
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for { set i 0 } { $i < $num_rows } { incr i } {
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set row_data_raw [get_report_panel_row -name $panel_name -row $i]
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set row_data [regsub -all , $row_data_raw ""]
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puts $fh [join $row_data ","]
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}
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}
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close $fh
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}
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# Dump names of all known panels
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proc do_dump_panelnames { } {
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set fh [open "panels.txt" w]
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set panel_names [get_report_panel_names]
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foreach panel_name $panel_names {
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puts $fh "$panel_name"
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}
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close $fh
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}
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proc do_map_analysis { ProjectName } {
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# Save synthesis results
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set RSyn1 "Synthesis||Synthesis Source Files Read"
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set RSyn2 "Synthesis||Partition \"root_partition\"||Synthesis Resource Usage Summary for Partition \"root_partition\""
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set RSyn3 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Resource Utilization by Entity"
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set RSyn4 "Synthesis||Partition \"root_partition\"||Synthesis RAM Summary for Partition \"root_partition\""
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set RSyn5 "Synthesis||Partition \"root_partition\"||Partition \"root_partition\" Optimization Results||Register Statistics||Registers Protected by Synthesis"
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set RSyn6 "Synthesis||Partition \"root_partition\"||Post-Synthesis Netlist Statistics for Partition \"root_partition\""
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panel_to_csv $RSyn1 "$ProjectName.syn.area.source_files.csv"
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panel_to_csv $RSyn2 "$ProjectName.syn.area.resource_summmary.csv"
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panel_to_csv $RSyn3 "$ProjectName.syn.area.resource_breakdown.csv"
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panel_to_csv $RSyn4 "$ProjectName.syn.area.ram_summary.csv"
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panel_to_csv $RSyn5 "$ProjectName.syn.area.regs_removed.csv"
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panel_to_csv $RSyn6 "$ProjectName.syn.area.stats.csv"
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}
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proc do_fit_analysis { ProjectName } {
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# Save par results
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set RPar1 "Fitter||Place Stage||Fitter Resource Usage Summary"
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set RPar2 "Fitter||Place Stage||Fitter Resource Utilization by Entity"
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set RPar3 "Fitter||Place Stage||Fitter Partition Statistics"
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set RPar4 "Fitter||Place Stage||Fitter RAM Summary"
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set RPar5 "Fitter||Plan Stage||Global & Other Fast Signals Summary"
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set RPar6 "Fitter||Place Stage||Non-Global High Fan-Out Signals"
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set RPar7 "Fitter||Route Stage||Routing Usage Summary"
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panel_to_csv $RPar1 "$ProjectName.fit.area.resource_summary.csv"
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panel_to_csv $RPar2 "$ProjectName.fit.area.resource_breakdown.csv"
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#panel_to_csv $RPar3 "$ProjectName.fit.area.stats.csv"
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panel_to_csv $RPar4 "$ProjectName.fit.area.ram_summary.csv"
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panel_to_csv $RPar5 "$ProjectName.fit.area.routing_global.csv"
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panel_to_csv $RPar6 "$ProjectName.fit.area.routing_high_fanout.csv"
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panel_to_csv $RPar7 "$ProjectName.fit.area.routing_summary.csv"
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}
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proc do_fit_analysis_timingsummary { ProjectName } {
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# Save timing results
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set RT1 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Fmax Summary"
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set RT2 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Setup Summary"
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set RT3 "TimeQuest Timing Analyzer||Slow 900mV 100C Model||Slow 900mV 100C Model Hold Summary"
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set RT4 "TimeQuest Timing Analyzer||Multicorner Timing Analysis Summary"
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panel_to_csv $RT1 "$ProjectName.fit.timing.summary.fmax.csv"
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panel_to_csv $RT2 "$ProjectName.fit.timing.summary.setup.csv"
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panel_to_csv $RT3 "$ProjectName.fit.timing.summary.hold.csv"
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panel_to_csv $RT4 "$ProjectName.fit.timing.summary.multicorner.csv"
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}
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project_open $ProjectName
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load_report
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# print available panels
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#do_dump_panelnames
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# => allows comparison of raw logic vs impact of routing delays
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if { $SynMode == "map" } {
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do_map_analysis $ProjectName
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# normal post-par analysis (includes routing congestion/physical placement constraints)
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} else {
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do_fit_analysis $ProjectName
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do_fit_analysis_timingsummary $ProjectName
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}
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unload_report
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project_close |