126 lines
3.0 KiB
Verilog
126 lines
3.0 KiB
Verilog
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`include "../VX_define.v"
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`define NUMBER_BANKS 8
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`define NUM_WORDS_PER_BLOCK 4
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`define ARM_UD_MODEL
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`timescale 1ns/1ps
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import "DPI-C" load_file = function void load_file(input string filename);
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import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr,
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output int instruction);
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import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
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input int o_m_read_addr,
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input int o_m_evict_addr,
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input logic o_m_valid,
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input reg[31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
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input logic o_m_read_or_write,
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// Rsp
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output reg[31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
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output logic i_m_ready);
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import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data);
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import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num);
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module vortex_tb (
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);
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int cycle_num;
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reg clk;
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reg reset;
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reg[31:0] icache_response_instruction;
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reg[31:0] icache_request_pc_address;
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// IO
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reg io_valid;
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reg[31:0] io_data;
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// Req
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reg [31:0] o_m_read_addr;
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reg [31:0] o_m_evict_addr;
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reg o_m_valid;
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reg [31:0] o_m_writedata[8 - 1:0][4-1:0];
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reg o_m_read_or_write;
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// Rsp
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reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
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reg i_m_ready;
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reg out_ebreak;
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reg[31:0] hi;
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integer temp;
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initial begin
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// $fdumpfile("vortex1.vcd");
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load_file("../../runtime/vortex_runtime.hex");
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$dumpvars(0, vortex_tb);
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reset = 1;
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clk = 0;
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#5 reset = 1;
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clk = 1;
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cycle_num = 0;
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end
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Vortex vortex(
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.clk (clk),
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.reset (reset),
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.icache_response_instruction(icache_response_instruction),
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.icache_request_pc_address (icache_request_pc_address),
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.io_valid (io_valid),
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.io_data (io_data),
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.o_m_read_addr (o_m_read_addr),
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.o_m_evict_addr (o_m_evict_addr),
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.o_m_valid (o_m_valid),
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.o_m_writedata (o_m_writedata),
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.o_m_read_or_write (o_m_read_or_write),
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.i_m_readdata (i_m_readdata),
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.i_m_ready (i_m_ready),
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.out_ebreak (out_ebreak)
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);
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always @(negedge clk) begin
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ibus_driver(clk, icache_request_pc_address, icache_response_instruction);
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dbus_driver(clk, o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, i_m_readdata, i_m_ready);
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io_handler (clk, io_valid, io_data);
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end
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always @(posedge clk) begin
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if (out_ebreak) begin
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gracefulExit(cycle_num);
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#40 $finish;
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end
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end
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always @(posedge clk) begin
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cycle_num = cycle_num + 1;
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end
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always @(clk, posedge reset) begin
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if (reset) begin
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reset = 0;
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clk = 0;
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end
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#5 clk <= ~clk;
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end
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endmodule
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