131 lines
4.5 KiB
Systemverilog
131 lines
4.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_smem_switch #(
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parameter NUM_REQS = 1,
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parameter DATA_SIZE = 1,
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parameter TAG_WIDTH = 1,
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parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH,
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parameter TAG_SEL_IDX = 0,
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parameter OUT_REG_REQ = 0,
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parameter OUT_REG_RSP = 0,
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parameter `STRING ARBITER = "R"
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) (
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input wire clk,
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input wire reset,
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VX_mem_bus_if.slave bus_in_if,
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VX_mem_bus_if.master bus_out_if [NUM_REQS]
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);
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localparam ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE));
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localparam DATA_WIDTH = (8 * DATA_SIZE);
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localparam LOG_NUM_REQS = `CLOG2(NUM_REQS);
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localparam TAG_OUT_WIDTH = TAG_WIDTH - LOG_NUM_REQS;
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localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH;
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localparam RSP_DATAW = TAG_OUT_WIDTH + DATA_WIDTH;
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wire [NUM_REQS-1:0] req_valid_out;
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_out;
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wire [NUM_REQS-1:0] req_ready_out;
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wire [REQ_DATAW-1:0] req_data_in;
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wire [TAG_OUT_WIDTH-1:0] req_tag_in;
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wire [`UP(LOG_NUM_REQS)-1:0] req_sel_in;
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VX_bits_remove #(
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.N (TAG_WIDTH),
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.S (LOG_NUM_REQS),
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.POS (TAG_SEL_IDX)
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) bits_remove (
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.data_in (bus_in_if.req_data.tag),
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.data_out (req_tag_in)
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);
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if (NUM_REQS > 1) begin
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assign req_sel_in = bus_in_if.req_data.tag[TAG_SEL_IDX +: LOG_NUM_REQS];
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end else begin
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assign req_sel_in = '0;
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end
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assign req_data_in = {req_tag_in, bus_in_if.req_data.addr, bus_in_if.req_data.rw, bus_in_if.req_data.byteen, bus_in_if.req_data.data};
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VX_stream_switch #(
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.NUM_OUTPUTS (NUM_REQS),
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.DATAW (REQ_DATAW),
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.OUT_REG (OUT_REG_REQ)
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) req_switch (
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.clk (clk),
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.reset (reset),
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.sel_in (req_sel_in),
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.valid_in (bus_in_if.req_valid),
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.ready_in (bus_in_if.req_ready),
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.data_in (req_data_in),
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.data_out (req_data_out),
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.valid_out (req_valid_out),
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.ready_out (req_ready_out)
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);
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign bus_out_if[i].req_valid = req_valid_out[i];
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assign {bus_out_if[i].req_data.tag, bus_out_if[i].req_data.addr, bus_out_if[i].req_data.rw, bus_out_if[i].req_data.byteen, bus_out_if[i].req_data.data} = req_data_out[i];
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assign req_ready_out[i] = bus_out_if[i].req_ready;
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end
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///////////////////////////////////////////////////////////////////////
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wire [NUM_REQS-1:0] rsp_valid_out;
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wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out;
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wire [NUM_REQS-1:0] rsp_ready_out;
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wire [RSP_DATAW-1:0] rsp_data_in;
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wire [TAG_OUT_WIDTH-1:0] rsp_tag_in;
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wire [`UP(LOG_NUM_REQS)-1:0] rsp_sel_in;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign rsp_valid_out[i] = bus_out_if[i].rsp_valid;
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assign rsp_data_out[i] = {bus_out_if[i].rsp_data.tag, bus_out_if[i].rsp_data.data};
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assign bus_out_if[i].rsp_ready = rsp_ready_out[i];
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end
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VX_stream_arb #(
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.NUM_INPUTS (NUM_REQS),
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.DATAW (RSP_DATAW),
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.ARBITER (ARBITER),
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.OUT_REG (OUT_REG_RSP)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_valid_out),
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.ready_in (rsp_ready_out),
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.data_in (rsp_data_out),
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.data_out (rsp_data_in),
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.sel_out (rsp_sel_in),
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.valid_out (bus_in_if.rsp_valid),
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.ready_out (bus_in_if.rsp_ready)
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);
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VX_bits_insert #(
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.N (TAG_OUT_WIDTH),
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.S (LOG_NUM_REQS),
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.POS (TAG_SEL_IDX)
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) bits_insert (
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.data_in (rsp_tag_in),
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.sel_in (rsp_sel_in),
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.data_out (bus_in_if.rsp_data.tag)
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);
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assign {rsp_tag_in, bus_in_if.rsp_data.data} = rsp_data_in;
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endmodule
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