125 lines
4.7 KiB
Verilog
125 lines
4.7 KiB
Verilog
`include "VX_define.vh"
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module VX_commit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_exu_to_cmt_if alu_commit_if,
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VX_exu_to_cmt_if lsu_commit_if,
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VX_exu_to_cmt_if mul_commit_if,
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VX_exu_to_cmt_if csr_commit_if,
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VX_fpu_to_cmt_if fpu_commit_if,
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VX_exu_to_cmt_if gpu_commit_if,
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// outputs
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VX_writeback_if writeback_if,
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VX_cmt_to_csr_if cmt_to_csr_if
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);
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// CSRs update
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wire [`NUM_EXS-1:0] commited_mask;
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assign commited_mask = {alu_commit_if.valid,
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lsu_commit_if.valid,
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csr_commit_if.valid,
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mul_commit_if.valid,
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fpu_commit_if.valid,
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gpu_commit_if.valid};
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wire [$clog2(`NUM_EXS+1)-1:0] num_commits;
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VX_countones #(
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.N(`NUM_EXS)
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) valids_counter (
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.valids(commited_mask),
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.count (num_commits)
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);
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fflags_t fflags;
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always @(*) begin
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fflags = 0;
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for (integer i = 0; i < `NUM_THREADS; i++) begin
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if (fpu_commit_if.tmask[i]) begin
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fflags.NX |= fpu_commit_if.fflags[i].NX;
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fflags.UF |= fpu_commit_if.fflags[i].UF;
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fflags.OF |= fpu_commit_if.fflags[i].OF;
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fflags.DZ |= fpu_commit_if.fflags[i].DZ;
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fflags.NV |= fpu_commit_if.fflags[i].NV;
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end
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end
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end
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fflags_t fflags_r;
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reg has_fflags_r;
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reg [`NW_BITS-1:0] wid_r;
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reg [$clog2(`NUM_EXS+1)-1:0] num_commits_r;
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reg csr_update_r;
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always @(posedge clk) begin
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csr_update_r <= (| commited_mask);
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fflags_r <= fflags;
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has_fflags_r <= fpu_commit_if.valid && fpu_commit_if.has_fflags;
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wid_r <= fpu_commit_if.wid;
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num_commits_r <= (num_commits << $clog2(`NUM_THREADS));
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end
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assign cmt_to_csr_if.valid = csr_update_r;
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assign cmt_to_csr_if.wid = wid_r;
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assign cmt_to_csr_if.num_commits = num_commits_r;
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assign cmt_to_csr_if.has_fflags = has_fflags_r;
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assign cmt_to_csr_if.fflags = fflags_r;
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// Writeback
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VX_writeback #(
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.CORE_ID(CORE_ID)
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) writeback (
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.clk (clk),
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.reset (reset),
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.alu_commit_if (alu_commit_if),
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.lsu_commit_if (lsu_commit_if),
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.csr_commit_if (csr_commit_if),
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.mul_commit_if (mul_commit_if),
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.fpu_commit_if (fpu_commit_if),
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.gpu_commit_if (gpu_commit_if),
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.writeback_if (writeback_if)
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_commit_if.valid && alu_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd, alu_commit_if.data);
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end
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if (lsu_commit_if.valid && lsu_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, lsu_commit_if.wid, lsu_commit_if.PC, lsu_commit_if.tmask, lsu_commit_if.wb, lsu_commit_if.rd, lsu_commit_if.data);
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end
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if (csr_commit_if.valid && csr_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=CSR, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.wb, csr_commit_if.rd, csr_commit_if.data);
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end
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if (mul_commit_if.valid && mul_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=MUL, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, mul_commit_if.wid, mul_commit_if.PC, mul_commit_if.tmask, mul_commit_if.wb, mul_commit_if.rd, mul_commit_if.data);
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end
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if (fpu_commit_if.valid && fpu_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd, fpu_commit_if.data);
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end
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if (gpu_commit_if.valid && gpu_commit_if.ready) begin
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$display("%t: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd, gpu_commit_if.data);
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end
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end
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`else
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`UNUSED_VAR(fpu_commit_if.PC)
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`endif
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endmodule
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