74 lines
1.7 KiB
Verilog
74 lines
1.7 KiB
Verilog
`include "VX_define.vh"
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// control module to support multi-cycle read for fp register
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module VX_gpr_fp_ctrl (
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input wire clk,
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input wire reset,
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input wire [`NUM_THREADS-1:0][31:0] rs1_data,
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input wire [`NUM_THREADS-1:0][31:0] rs2_data,
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VX_gpr_req_if gpr_req_if,
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// outputs
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output wire [`NW_BITS+`NR_BITS-1:0] raddr1,
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VX_gpr_rsp_if gpr_rsp_if
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);
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reg [`NUM_THREADS-1:0][31:0] rsp_rs1_data, rsp_rs2_data, rsp_rs3_data;
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reg rsp_valid;
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reg [31:0] rsp_pc;
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reg [`NW_BITS-1:0] rsp_wid;
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reg read_rs1;
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wire rs3_delay = gpr_req_if.valid && gpr_req_if.use_rs3 && read_rs1;
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wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready;
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always @(posedge clk) begin
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if (reset) begin
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rsp_valid <= 0;
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rsp_pc <= 0;
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rsp_rs1_data <= 0;
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rsp_rs2_data <= 0;
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rsp_rs3_data <= 0;
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rsp_wid <= 0;
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read_rs1 <= 1;
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end else begin
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if (rs3_delay) begin
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read_rs1 <= 0;
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rsp_wid <= gpr_req_if.wid;
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end else if (read_fire) begin
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read_rs1 <= 1;
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end
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rsp_valid <= gpr_req_if.valid;
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rsp_wid <= gpr_req_if.wid;
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rsp_pc <= gpr_req_if.PC;
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if (read_rs1) begin
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rsp_rs1_data <= rs1_data;
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end
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rsp_rs2_data <= rs2_data;
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rsp_rs3_data <= rs1_data;
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assert(read_rs1 || rsp_wid == gpr_req_if.wid);
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end
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end
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always @(posedge clk) begin
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end
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// outputs
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wire [`NR_BITS-1:0] rs1 = read_rs1 ? gpr_req_if.rs1 : gpr_req_if.rs3;
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assign raddr1 = {gpr_req_if.wid, rs1};
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assign gpr_req_if.ready = ~rs3_delay;
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assign gpr_rsp_if.valid = rsp_valid;
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assign gpr_rsp_if.wid = rsp_wid;
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assign gpr_rsp_if.PC = rsp_pc;
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assign gpr_rsp_if.rs1_data = rsp_rs1_data;
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assign gpr_rsp_if.rs2_data = rsp_rs2_data;
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assign gpr_rsp_if.rs3_data = rsp_rs3_data;
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endmodule |