400 lines
17 KiB
Systemverilog
400 lines
17 KiB
Systemverilog
`ifndef VX_SCOPE
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`define VX_SCOPE
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`ifdef SCOPE
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`define SCOPE_SIGNALS_DATA_LIST \
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scope_dram_req_addr, \
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scope_dram_req_rw, \
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scope_dram_req_byteen, \
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scope_dram_req_data, \
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scope_dram_req_tag, \
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scope_dram_rsp_data, \
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scope_dram_rsp_tag, \
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scope_snp_req_addr, \
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scope_snp_req_invalidate, \
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scope_snp_req_tag, \
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scope_snp_rsp_tag, \
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scope_icache_req_wid, \
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scope_icache_req_addr, \
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scope_icache_req_tag, \
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scope_icache_rsp_data, \
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scope_icache_rsp_tag, \
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scope_dcache_req_wid, \
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scope_dcache_req_pc, \
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scope_dcache_req_addr, \
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scope_dcache_req_rw, \
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scope_dcache_req_byteen, \
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scope_dcache_req_data, \
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scope_dcache_req_tag, \
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scope_dcache_rsp_data, \
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scope_dcache_rsp_tag, \
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scope_issue_wid, \
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scope_issue_tmask, \
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scope_issue_pc, \
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scope_issue_ex_type, \
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scope_issue_op_type, \
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scope_issue_op_mod, \
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scope_issue_wb, \
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scope_issue_rd, \
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scope_issue_rs1, \
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scope_issue_rs2, \
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scope_issue_rs3, \
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scope_issue_imm, \
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scope_issue_rs1_is_pc, \
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scope_issue_rs2_is_imm, \
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scope_gpr_rsp_wid, \
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scope_gpr_rsp_pc, \
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scope_gpr_rsp_a, \
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scope_gpr_rsp_b, \
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scope_gpr_rsp_c, \
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scope_writeback_wid, \
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scope_writeback_pc, \
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scope_writeback_rd, \
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scope_writeback_data, \
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scope_bank_addr_st0, \
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scope_bank_addr_st1, \
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scope_bank_addr_st2, \
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scope_bank_is_mrvq_st1, \
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scope_bank_miss_st1, \
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scope_bank_dirty_st1, \
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scope_bank_force_miss_st1,
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`define SCOPE_SIGNALS_UPD_LIST \
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scope_dram_req_valid, \
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scope_dram_req_ready, \
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scope_dram_rsp_valid, \
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scope_dram_rsp_ready, \
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scope_snp_req_valid, \
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scope_snp_req_ready, \
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scope_snp_rsp_valid, \
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scope_snp_rsp_ready, \
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scope_icache_req_valid, \
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scope_icache_req_ready, \
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scope_icache_rsp_valid, \
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scope_icache_rsp_ready, \
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scope_dcache_req_valid, \
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scope_dcache_req_ready, \
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scope_dcache_rsp_valid, \
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scope_dcache_rsp_ready, \
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scope_bank_valid_st0, \
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scope_bank_valid_st1, \
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scope_bank_valid_st2, \
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scope_bank_stall_pipe, \
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scope_issue_valid, \
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scope_issue_ready, \
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scope_gpr_rsp_valid, \
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scope_writeback_valid, \
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scope_scoreboard_delay, \
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scope_gpr_delay, \
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scope_execute_delay, \
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scope_busy
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`define SCOPE_SIGNALS_DECL \
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wire scope_dram_req_valid; \
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wire [31:0] scope_dram_req_addr; \
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wire scope_dram_req_rw; \
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wire [15:0] scope_dram_req_byteen; \
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wire [127:0] scope_dram_req_data; \
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wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
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wire scope_dram_req_ready; \
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wire scope_dram_rsp_valid; \
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wire [127:0] scope_dram_rsp_data; \
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wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
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wire scope_dram_rsp_ready; \
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wire scope_snp_req_valid; \
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wire [31:0] scope_snp_req_addr; \
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wire scope_snp_req_invalidate; \
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wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
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wire scope_snp_req_ready; \
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wire scope_snp_rsp_valid; \
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wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
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wire scope_icache_req_valid; \
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wire [`NW_BITS-1:0] scope_icache_req_wid; \
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wire [31:0] scope_icache_req_addr; \
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wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag; \
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wire scope_icache_req_ready; \
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wire scope_icache_rsp_valid; \
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wire [31:0] scope_icache_rsp_data; \
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wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag; \
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wire scope_icache_rsp_ready; \
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wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \
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wire [`NW_BITS-1:0] scope_dcache_req_wid; \
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wire [31:0] scope_dcache_req_pc; \
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wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr; \
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wire scope_dcache_req_rw; \
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wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen; \
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wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data; \
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wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag; \
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wire scope_dcache_req_ready; \
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wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \
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wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data; \
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wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag; \
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wire scope_dcache_rsp_ready; \
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wire scope_snp_rsp_ready; \
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wire [`NW_BITS-1:0] scope_issue_wid; \
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wire [`NUM_THREADS-1:0] scope_issue_tmask; \
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wire [31:0] scope_issue_pc; \
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wire [`EX_BITS-1:0] scope_issue_ex_type; \
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wire [`OP_BITS-1:0] scope_issue_op_type; \
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wire [`MOD_BITS-1:0] scope_issue_op_mod; \
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wire scope_issue_wb; \
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wire [`NR_BITS-1:0] scope_issue_rd; \
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wire [`NR_BITS-1:0] scope_issue_rs1; \
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wire [`NR_BITS-1:0] scope_issue_rs2; \
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wire [`NR_BITS-1:0] scope_issue_rs3; \
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wire [31:0] scope_issue_imm; \
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wire scope_issue_rs1_is_pc; \
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wire scope_issue_rs2_is_imm; \
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wire scope_gpr_rsp_valid; \
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wire [`NW_BITS-1:0] scope_gpr_rsp_wid; \
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wire [31:0] scope_gpr_rsp_pc; \
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wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a; \
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wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b; \
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wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c; \
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wire scope_writeback_valid; \
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wire [`NW_BITS-1:0] scope_writeback_wid; \
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wire [31:0] scope_writeback_pc; \
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wire [`NR_BITS-1:0] scope_writeback_rd; \
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wire [`NUM_THREADS-1:0][31:0] scope_writeback_data; \
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wire scope_bank_valid_st0; \
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wire scope_bank_valid_st1; \
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wire scope_bank_valid_st2; \
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wire [31:0] scope_bank_addr_st0; \
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wire [31:0] scope_bank_addr_st1; \
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wire [31:0] scope_bank_addr_st2; \
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wire scope_bank_is_mrvq_st1; \
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wire scope_bank_miss_st1; \
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wire scope_bank_dirty_st1; \
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wire scope_bank_force_miss_st1; \
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wire scope_bank_stall_pipe; \
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wire scope_issue_valid; \
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wire scope_issue_ready; \
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wire scope_scoreboard_delay; \
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wire scope_gpr_delay; \
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wire scope_execute_delay; \
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wire scope_busy;
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`define SCOPE_SIGNALS_ISTAGE_IO \
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output wire scope_icache_req_valid, \
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output wire [`NW_BITS-1:0] scope_icache_req_wid, \
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output wire [31:0] scope_icache_req_addr, \
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output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag, \
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output wire scope_icache_req_ready, \
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output wire scope_icache_rsp_valid, \
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output wire [31:0] scope_icache_rsp_data, \
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output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag, \
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output wire scope_icache_rsp_ready,
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`define SCOPE_SIGNALS_LSU_IO \
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output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \
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output wire [`NW_BITS-1:0] scope_dcache_req_wid, \
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output wire [31:0] scope_dcache_req_pc, \
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output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr, \
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output wire scope_dcache_req_rw, \
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output wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen, \
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output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data, \
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output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag, \
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output wire scope_dcache_req_ready, \
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output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \
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output wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data, \
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output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag, \
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output wire scope_dcache_rsp_ready,
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`define SCOPE_SIGNALS_CACHE_IO \
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output wire scope_bank_valid_st0, \
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output wire scope_bank_valid_st1, \
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output wire scope_bank_valid_st2, \
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output wire [31:0] scope_bank_addr_st0, \
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output wire [31:0] scope_bank_addr_st1, \
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output wire [31:0] scope_bank_addr_st2, \
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output wire scope_bank_is_mrvq_st1, \
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output wire scope_bank_miss_st1, \
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output wire scope_bank_dirty_st1, \
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output wire scope_bank_force_miss_st1, \
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output wire scope_bank_stall_pipe,
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`define SCOPE_SIGNALS_ISSUE_IO \
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output wire scope_issue_valid, \
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output wire [`NW_BITS-1:0] scope_issue_wid, \
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output wire [`NUM_THREADS-1:0] scope_issue_tmask, \
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output wire [31:0] scope_issue_pc, \
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output wire [`EX_BITS-1:0] scope_issue_ex_type, \
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output wire [`OP_BITS-1:0] scope_issue_op_type, \
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output wire [`MOD_BITS-1:0] scope_issue_op_mod, \
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output wire scope_issue_wb, \
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output wire [`NR_BITS-1:0] scope_issue_rd, \
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output wire [`NR_BITS-1:0] scope_issue_rs1, \
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output wire [`NR_BITS-1:0] scope_issue_rs2, \
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output wire [`NR_BITS-1:0] scope_issue_rs3, \
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output wire [31:0] scope_issue_imm, \
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output wire scope_issue_rs1_is_pc, \
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output wire scope_issue_rs2_is_imm, \
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output wire scope_writeback_valid, \
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output wire scope_gpr_rsp_valid, \
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output wire [`NW_BITS-1:0] scope_gpr_rsp_wid, \
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output wire [31:0] scope_gpr_rsp_pc, \
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output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a, \
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output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b, \
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output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c, \
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output wire [`NW_BITS-1:0] scope_writeback_wid, \
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output wire [31:0] scope_writeback_pc, \
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output wire [`NR_BITS-1:0] scope_writeback_rd, \
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output wire [`NUM_THREADS-1:0][31:0] scope_writeback_data, \
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output wire scope_issue_ready, \
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output wire scope_scoreboard_delay, \
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output wire scope_gpr_delay, \
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output wire scope_execute_delay,
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`define SCOPE_SIGNALS_EXECUTE_IO
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`define SCOPE_SIGNALS_ISTAGE_BIND \
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.scope_icache_req_valid (scope_icache_req_valid), \
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.scope_icache_req_wid (scope_icache_req_wid), \
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.scope_icache_req_addr (scope_icache_req_addr), \
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.scope_icache_req_tag (scope_icache_req_tag), \
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.scope_icache_req_ready (scope_icache_req_ready), \
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.scope_icache_rsp_valid (scope_icache_rsp_valid), \
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.scope_icache_rsp_data (scope_icache_rsp_data), \
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.scope_icache_rsp_tag (scope_icache_rsp_tag), \
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.scope_icache_rsp_ready (scope_icache_rsp_ready),
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`define SCOPE_SIGNALS_LSU_BIND \
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.scope_dcache_req_valid (scope_dcache_req_valid), \
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.scope_dcache_req_wid (scope_dcache_req_wid), \
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.scope_dcache_req_pc (scope_dcache_req_pc), \
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.scope_dcache_req_addr (scope_dcache_req_addr), \
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.scope_dcache_req_rw (scope_dcache_req_rw), \
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.scope_dcache_req_byteen(scope_dcache_req_byteen), \
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.scope_dcache_req_data (scope_dcache_req_data), \
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.scope_dcache_req_tag (scope_dcache_req_tag), \
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.scope_dcache_req_ready (scope_dcache_req_ready), \
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.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
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.scope_dcache_rsp_data (scope_dcache_rsp_data), \
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.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
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.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
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`define SCOPE_SIGNALS_CACHE_BIND \
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.scope_bank_valid_st0 (scope_bank_valid_st0), \
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.scope_bank_valid_st1 (scope_bank_valid_st1), \
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.scope_bank_valid_st2 (scope_bank_valid_st2), \
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.scope_bank_addr_st0 (scope_bank_addr_st0), \
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.scope_bank_addr_st1 (scope_bank_addr_st1), \
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.scope_bank_addr_st2 (scope_bank_addr_st2), \
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.scope_bank_is_mrvq_st1 (scope_bank_is_mrvq_st1), \
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.scope_bank_miss_st1 (scope_bank_miss_st1), \
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.scope_bank_dirty_st1 (scope_bank_dirty_st1), \
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.scope_bank_force_miss_st1(scope_bank_force_miss_st1), \
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.scope_bank_stall_pipe (scope_bank_stall_pipe),
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`define SCOPE_SIGNALS_CACHE_UNBIND \
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/* verilator lint_off PINCONNECTEMPTY */ \
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.scope_bank_valid_st0 (), \
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.scope_bank_valid_st1 (), \
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.scope_bank_valid_st2 (), \
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.scope_bank_addr_st0 (), \
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.scope_bank_addr_st1 (), \
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.scope_bank_addr_st2 (), \
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.scope_bank_is_mrvq_st1 (), \
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.scope_bank_miss_st1 (), \
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.scope_bank_dirty_st1 (), \
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.scope_bank_force_miss_st1 (), \
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.scope_bank_stall_pipe (), \
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/* verilator lint_on PINCONNECTEMPTY */
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`define SCOPE_SIGNALS_CACHE_BANK_SELECT \
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/* verilator lint_off UNUSED */ \
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wire [NUM_BANKS-1:0] scope_per_bank_valid_st0; \
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wire [NUM_BANKS-1:0] scope_per_bank_valid_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_valid_st2; \
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wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st0; \
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wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st1; \
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wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st2; \
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wire [NUM_BANKS-1:0] scope_per_bank_is_mrvq_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_miss_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_dirty_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_force_miss_st1; \
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wire [NUM_BANKS-1:0] scope_per_bank_stall_pipe; \
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/* verilator lint_on UNUSED */ \
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assign scope_bank_valid_st0 = scope_per_bank_valid_st0[0]; \
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assign scope_bank_valid_st1 = scope_per_bank_valid_st1[0]; \
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assign scope_bank_valid_st2 = scope_per_bank_valid_st2[0]; \
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assign scope_bank_addr_st0 = scope_per_bank_addr_st0[0]; \
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assign scope_bank_addr_st1 = scope_per_bank_addr_st1[0]; \
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assign scope_bank_addr_st2 = scope_per_bank_addr_st2[0]; \
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assign scope_bank_is_mrvq_st1 = scope_per_bank_is_mrvq_st1[0]; \
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assign scope_bank_miss_st1 = scope_per_bank_miss_st1[0]; \
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assign scope_bank_dirty_st1 = scope_per_bank_dirty_st1[0]; \
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assign scope_bank_force_miss_st1 = scope_per_bank_force_miss_st1[0]; \
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assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0];
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`define SCOPE_SIGNALS_CACHE_BANK_BIND \
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.scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \
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.scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \
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.scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \
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.scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \
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.scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \
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.scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \
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.scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \
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.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
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.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
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.scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \
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.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),
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`define SCOPE_SIGNALS_ISSUE_BIND \
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.scope_issue_valid (scope_issue_valid), \
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.scope_issue_wid (scope_issue_wid), \
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.scope_issue_tmask (scope_issue_tmask), \
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.scope_issue_pc (scope_issue_pc), \
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.scope_issue_ex_type (scope_issue_ex_type), \
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.scope_issue_op_type (scope_issue_op_type), \
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.scope_issue_op_mod (scope_issue_op_mod), \
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.scope_issue_wb (scope_issue_wb), \
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.scope_issue_rd (scope_issue_rd), \
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.scope_issue_rs1 (scope_issue_rs1), \
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.scope_issue_rs2 (scope_issue_rs2), \
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.scope_issue_rs3 (scope_issue_rs3), \
|
|
.scope_issue_imm (scope_issue_imm), \
|
|
.scope_issue_rs1_is_pc (scope_issue_rs1_is_pc), \
|
|
.scope_issue_rs2_is_imm (scope_issue_rs2_is_imm), \
|
|
.scope_writeback_valid (scope_writeback_valid), \
|
|
.scope_writeback_wid (scope_writeback_wid), \
|
|
.scope_writeback_pc (scope_writeback_pc), \
|
|
.scope_writeback_rd (scope_writeback_rd), \
|
|
.scope_writeback_data (scope_writeback_data), \
|
|
.scope_issue_ready (scope_issue_ready), \
|
|
.scope_gpr_rsp_valid (scope_gpr_rsp_valid), \
|
|
.scope_gpr_rsp_wid (scope_gpr_rsp_wid), \
|
|
.scope_gpr_rsp_pc (scope_gpr_rsp_pc), \
|
|
.scope_gpr_rsp_a (scope_gpr_rsp_a), \
|
|
.scope_gpr_rsp_b (scope_gpr_rsp_b), \
|
|
.scope_gpr_rsp_c (scope_gpr_rsp_c), \
|
|
.scope_scoreboard_delay (scope_scoreboard_delay), \
|
|
.scope_gpr_delay (scope_gpr_delay), \
|
|
.scope_execute_delay (scope_execute_delay), \
|
|
|
|
`define SCOPE_SIGNALS_EXECUTE_BIND
|
|
|
|
`define SCOPE_ASSIGN(d,s) assign d = s
|
|
`else
|
|
`define SCOPE_SIGNALS_ISTAGE_IO
|
|
`define SCOPE_SIGNALS_LSU_IO
|
|
`define SCOPE_SIGNALS_CACHE_IO
|
|
`define SCOPE_SIGNALS_ISSUE_IO
|
|
`define SCOPE_SIGNALS_EXECUTE_IO
|
|
|
|
`define SCOPE_SIGNALS_ISTAGE_BIND
|
|
`define SCOPE_SIGNALS_LSU_BIND
|
|
`define SCOPE_SIGNALS_CACHE_BIND
|
|
`define SCOPE_SIGNALS_ISSUE_BIND
|
|
`define SCOPE_SIGNALS_EXECUTE_BIND
|
|
|
|
`define SCOPE_SIGNALS_CACHE_UNBIND
|
|
`define SCOPE_SIGNALS_CACHE_BANK_SELECT
|
|
`define SCOPE_SIGNALS_CACHE_BANK_BIND
|
|
|
|
`define SCOPE_ASSIGN(d,s)
|
|
`endif
|
|
|
|
// VX_SCOPE
|
|
`endif |