96 lines
4.2 KiB
Verilog
96 lines
4.2 KiB
Verilog
`include "VX_define.vh"
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module VX_writeback #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_exu_to_cmt_if alu_commit_if,
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VX_exu_to_cmt_if lsu_commit_if,
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VX_exu_to_cmt_if csr_commit_if,
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VX_exu_to_cmt_if mul_commit_if,
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VX_fpu_to_cmt_if fpu_commit_if,
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VX_exu_to_cmt_if gpu_commit_if,
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// outputs
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VX_writeback_if writeback_if
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);
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wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
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wire lsu_valid = lsu_commit_if.valid && lsu_commit_if.wb;
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wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;
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wire mul_valid = mul_commit_if.valid && mul_commit_if.wb;
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wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
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wire wb_valid;
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wire [`NW_BITS-1:0] wb_wid;
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wire [`NUM_THREADS-1:0] wb_tmask;
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wire [`NR_BITS-1:0] wb_rd;
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wire [`NUM_THREADS-1:0][31:0] wb_data;
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assign wb_valid = alu_valid ? alu_commit_if.valid :
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lsu_valid ? lsu_commit_if.valid :
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csr_valid ? csr_commit_if.valid :
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mul_valid ? mul_commit_if.valid :
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fpu_valid ? fpu_commit_if.valid :
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0;
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assign wb_wid = alu_valid ? alu_commit_if.wid :
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lsu_valid ? lsu_commit_if.wid :
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csr_valid ? csr_commit_if.wid :
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mul_valid ? mul_commit_if.wid :
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fpu_valid ? fpu_commit_if.wid :
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0;
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assign wb_tmask = alu_valid ? alu_commit_if.tmask :
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lsu_valid ? lsu_commit_if.tmask :
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csr_valid ? csr_commit_if.tmask :
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mul_valid ? mul_commit_if.tmask :
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fpu_valid ? fpu_commit_if.tmask :
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0;
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assign wb_rd = alu_valid ? alu_commit_if.rd :
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lsu_valid ? lsu_commit_if.rd :
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csr_valid ? csr_commit_if.rd :
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mul_valid ? mul_commit_if.rd :
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fpu_valid ? fpu_commit_if.rd :
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0;
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assign wb_data = alu_valid ? alu_commit_if.data :
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lsu_valid ? lsu_commit_if.data :
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csr_valid ? csr_commit_if.data :
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mul_valid ? mul_commit_if.data :
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fpu_valid ? fpu_commit_if.data :
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0;
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always @(*) assert(writeback_if.ready);
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wire stall = 0/*~writeback_if.ready && writeback_if.valid*/;
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32))
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) wb_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (1'b0),
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.in ({wb_valid, wb_wid, wb_tmask, wb_rd, wb_data}),
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.out ({writeback_if.valid, writeback_if.wid, writeback_if.tmask, writeback_if.rd, writeback_if.data})
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);
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assign alu_commit_if.ready = !stall;
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assign lsu_commit_if.ready = !stall && !alu_valid;
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assign csr_commit_if.ready = !stall && !alu_valid && !lsu_valid;
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assign mul_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid;
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assign fpu_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid && !mul_valid;
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assign gpu_commit_if.ready = 1'b1;
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// special workaround to get RISC-V tests Pass/Fail status
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reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;
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always @(posedge clk) begin
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if (writeback_if.valid && writeback_if.ready) begin
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last_wb_value[writeback_if.rd] <= writeback_if.data[0];
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end
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end
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endmodule |