28 lines
668 B
Verilog
28 lines
668 B
Verilog
`include "VX_platform.vh"
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module VX_priority_encoder #(
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parameter N = 1
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) (
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input wire [N-1:0] data_in,
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output wire [`LOG2UP(N)-1:0] data_out,
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output wire valid_out
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);
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reg [`LOG2UP(N)-1:0] data_out_r;
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reg valid_out_r;
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always @(*) begin
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data_out_r = 0;
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valid_out_r = 0;
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for (integer i = 0; i < N; i++) begin
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if (data_in[i]) begin
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data_out_r = `LOG2UP(N)'(i);
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valid_out_r = 1;
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break;
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end
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end
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end
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assign data_out = data_out_r;
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assign valid_out = valid_out_r;
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endmodule |