18 lines
391 B
Verilog
18 lines
391 B
Verilog
`ifndef VX_CACHE_DRAM_RSP_IF
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`define VX_CACHE_DRAM_RSP_IF
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`include "../cache/VX_cache_config.vh"
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interface VX_cache_dram_rsp_if #(
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parameter DRAM_LINE_WIDTH = 1,
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parameter DRAM_TAG_WIDTH = 1
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) ();
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wire valid;
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wire [DRAM_LINE_WIDTH-1:0] data;
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wire [DRAM_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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`endif |