Blaise Tine 4d55118545 cache pipeline optimization - moved tag access to stage0

2021-01-03 23:10:41 -05:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

old_rtl

refactoring fixes

2020-04-14 19:39:59 -04:00

opae

FPU float<->int conversion optimization

2020-12-29 15:37:45 -08:00

rtl

cache pipeline optimization - moved tag access to stage0

2021-01-03 23:10:41 -05:00

scripts

cache pipeline optimization - moved tag access to stage0

2021-01-03 23:10:41 -05:00

simulate

using single-port block ram for cache tags, restoring core reset signal

2021-01-02 19:53:41 -08:00

syn

FPU float<->int conversion optimization

2020-12-29 15:37:45 -08:00

unit_tests

scratchpad optimization for stack access using custom bank offset aligned to stack size

2021-01-02 16:00:00 -05:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

scope refactoring

2020-10-03 18:53:21 -04:00