92 lines
2.7 KiB
Makefile
92 lines
2.7 KiB
Makefile
#CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
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CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
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CFLAGS += -I../../../../hw
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# control RTL debug print states
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_SNP
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
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DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
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DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
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DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
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DBG_PRINT_FLAGS += -DDBG_CORE_REQ_INFO
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DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
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DBG_FLAGS += $(DBG_PRINT_FLAGS)
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DBG_FLAGS += -DDBG_CORE_REQ_INFO
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#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
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#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
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CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
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#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
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DEBUG=1
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#SCOPE=1
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CFLAGS += -fPIC
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CFLAGS += -DUSE_RTLSIM $(CONFIGS)
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CFLAGS += -DDUMP_PERF_STATS
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LDFLAGS += -shared -pthread
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# LDFLAGS += -dynamiclib -pthread
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TOP = vortex_afu_shim
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RTL_DIR=../../../hw/rtl
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SRCS = fpga.cpp opae_sim.cpp
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SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp
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FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/svdpi -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
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VL_FLAGS += -Wno-DECLFILENAME
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VL_FLAGS += --x-initial unique --x-assign unique
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VL_FLAGS += verilator.vlt
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# Enable Verilator multithreaded simulation
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#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
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#VL_FLAGS += --threads $(THREADS)
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# Debugigng
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ifdef DEBUG
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VL_FLAGS += -DVCD_OUTPUT --assert --trace $(DBG_FLAGS)
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CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
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else
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VL_FLAGS += -DNDEBUG
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CFLAGS += -DNDEBUG
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endif
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# Enable scope analyzer
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ifdef SCOPE
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VL_FLAGS += -DSCOPE
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CFLAGS += -DSCOPE
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SCOPE_CFG = scope
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endif
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VL_FLAGS += -DNOPAE
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CFLAGS += -DNOPAE
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RTL_INCLUDE += -I../../../hw/opae -I../../../hw/opae/ccip
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PROJECT = libopae-c-vlsim.so
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all: $(PROJECT)
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# generate scope data
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scope: ../../../hw/scripts/scope.json
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../../../hw/scripts/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl ../../../hw/rtl/scope-defs.vh ../../../hw/scripts/scope.json
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$(PROJECT): $(SRCS) $(SCOPE_CFG)
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verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
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OPT_FAST="-O0 -g" make -j -C obj_dir -f V$(TOP).mk
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clean:
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rm -rf $(PROJECT) obj_dir
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