125 lines
4.8 KiB
Verilog
125 lines
4.8 KiB
Verilog
`include "VX_define.vh"
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module VX_alu_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_alu_req_if alu_req_if,
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// Outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_exu_to_cmt_if alu_commit_if
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);
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reg [`NUM_THREADS-1:0][31:0] alu_result;
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reg [`NUM_THREADS-1:0][31:0] add_result;
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reg [`NUM_THREADS-1:0][32:0] sub_result;
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reg [`NUM_THREADS-1:0][31:0] shr_result;
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reg [`NUM_THREADS-1:0][31:0] msc_result;
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wire is_br_op = alu_req_if.is_br_op;
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wire [`ALU_BITS-1:0] alu_op = `ALU_OP(alu_req_if.op_type);
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wire [`BR_BITS-1:0] br_op = `BR_OP(alu_req_if.op_type);
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wire alu_signed = `ALU_SIGNED(alu_op);
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wire [1:0] alu_op_class = `ALU_OP_CLASS(alu_op);
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wire is_sub = (alu_op == `ALU_SUB);
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.rs1_is_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.rs2_is_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.rs2_is_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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always @(*) begin
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add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] sub_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
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wire [32:0] sub_in2 = {alu_signed & alu_in2_less[i][31], alu_in2_less[i]};
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always @(*) begin
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sub_result[i] = $signed(sub_in1) - $signed(sub_in2);
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] shr_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
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`IGNORE_WARNINGS_BEGIN
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wire [32:0] shr_value = $signed(shr_in1) >>> alu_in2_imm[i][4:0];
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`IGNORE_WARNINGS_END
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always @(*) begin
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shr_result[i] = shr_value[31:0];
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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always @(*) begin
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case (alu_op)
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`ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i];
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`ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i];
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`ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i];
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//`ALU_SLL,
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default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0];
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endcase
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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always @(*) begin
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case (alu_op_class)
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0: alu_result[i] = add_result[i];
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1: alu_result[i] = {31'b0, sub_result[i][32]};
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2: alu_result[i] = is_sub ? sub_result[i][31:0] : shr_result[i];
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default: alu_result[i] = msc_result[i];
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endcase
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end
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end
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wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR);
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wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result;
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wire [31:0] br_dest = add_result[alu_req_if.tid];
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wire [32:0] cmp_result = sub_result[alu_req_if.tid];
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wire [32:0] cmp_result_r;
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wire is_br_op_r;
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`IGNORE_WARNINGS_BEGIN
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wire [`BR_BITS-1:0] br_op_r;
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`IGNORE_WARNINGS_END
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// output
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wire stall_out = ~alu_commit_if.ready && alu_commit_if.valid;
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 32 + 33)
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) alu_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_out),
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.flush (1'b0),
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.in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, br_dest, cmp_result}),
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.out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, br_op_r, branch_ctl_if.dest, cmp_result_r})
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);
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wire is_less = cmp_result_r[32];
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wire is_equal = ~(| cmp_result_r[31:0]);
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wire br_neg = `BR_NEG(br_op_r);
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wire br_less = `BR_LESS(br_op_r);
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wire br_static = `BR_STATIC(br_op_r);
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wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static;
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assign branch_ctl_if.valid = alu_commit_if.valid && alu_commit_if.ready && is_br_op_r;
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assign branch_ctl_if.wid = alu_commit_if.wid;
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assign branch_ctl_if.taken = br_taken;
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// can accept new request?
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assign alu_req_if.ready = ~stall_out;
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endmodule |