50 lines
1.9 KiB
Verilog
50 lines
1.9 KiB
Verilog
`include "VX_define.vh"
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module VX_dcache_arb (
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// input request
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VX_cache_core_req_if core_req_in_if,
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// output 0 request
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VX_cache_core_req_if core_req_out0_if,
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// output 1 request
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VX_cache_core_req_if core_req_out1_if,
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// input 0 response
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VX_cache_core_rsp_if core_rsp_in0_if,
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// input 1 response
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VX_cache_core_rsp_if core_rsp_in1_if,
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// output response
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VX_cache_core_rsp_if core_rsp_out_if,
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// bus select
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input wire select_req,
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input wire select_rsp
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);
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// select request
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assign core_req_out0_if.valid = core_req_in_if.valid & {`NUM_THREADS{~select_req}};
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assign core_req_out0_if.rw = core_req_in_if.rw;
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assign core_req_out0_if.byteen = core_req_in_if.byteen;
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assign core_req_out0_if.addr = core_req_in_if.addr;
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assign core_req_out0_if.data = core_req_in_if.data;
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assign core_req_out0_if.tag = core_req_in_if.tag;
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assign core_req_out1_if.valid = core_req_in_if.valid & {`NUM_THREADS{select_req}};
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assign core_req_out1_if.rw = core_req_in_if.rw;
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assign core_req_out1_if.byteen = core_req_in_if.byteen;
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assign core_req_out1_if.addr = core_req_in_if.addr;
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assign core_req_out1_if.data = core_req_in_if.data;
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assign core_req_out1_if.tag = core_req_in_if.tag;
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assign core_req_in_if.ready = select_req ? core_req_out1_if.ready : core_req_out0_if.ready;
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// select response
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assign core_rsp_out_if.valid = select_rsp ? core_rsp_in1_if.valid : core_rsp_in0_if.valid;
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assign core_rsp_out_if.data = select_rsp ? core_rsp_in1_if.data : core_rsp_in0_if.data;
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assign core_rsp_out_if.tag = select_rsp ? core_rsp_in1_if.tag : core_rsp_in0_if.tag;
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assign core_rsp_in0_if.ready = core_rsp_out_if.ready && ~select_rsp;
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assign core_rsp_in1_if.ready = core_rsp_out_if.ready && select_rsp;
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endmodule |