17 lines
246 B
Verilog
17 lines
246 B
Verilog
`ifndef VX_CSR_TO_ISSUE_IF
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`define VX_CSR_TO_ISSUE_IF
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`include "VX_define.vh"
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`ifndef EXTF_F_ENABLE
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`IGNORE_WARNINGS_BEGIN
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`endif
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interface VX_csr_to_issue_if ();
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wire [`NW_BITS-1:0] wid;
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wire [`FRM_BITS-1:0] frm;
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endinterface
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`endif |