c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
86 lines
2.2 KiB
C++
86 lines
2.2 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <simobject.h>
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#include "dcrs.h"
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#include "arch.h"
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#include "cache_cluster.h"
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#include "shared_mem.h"
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#include "core.h"
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#include "constants.h"
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namespace vortex {
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class ProcessorImpl;
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class Cluster : public SimObject<Cluster> {
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public:
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struct PerfStats {
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CacheSim::PerfStats icache;
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CacheSim::PerfStats dcache;
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SharedMem::PerfStats sharedmem;
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CacheSim::PerfStats l2cache;
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PerfStats& operator+=(const PerfStats& rhs) {
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this->icache += rhs.icache;
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this->dcache += rhs.dcache;
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this->sharedmem += rhs.sharedmem;
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this->l2cache += rhs.l2cache;
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return *this;
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}
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};
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SimPort<MemReq> mem_req_port;
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SimPort<MemRsp> mem_rsp_port;
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Cluster(const SimContext& ctx,
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uint32_t cluster_id,
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ProcessorImpl* processor,
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const Arch &arch,
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const DCRS &dcrs);
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~Cluster();
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void reset();
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void tick();
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void attach_ram(RAM* ram);
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bool running() const;
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bool check_exit(Word* exitcode, bool riscv_test) const;
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void barrier(uint32_t bar_id, uint32_t count, uint32_t core_id);
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ProcessorImpl* processor() const;
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Cluster::PerfStats perf_stats() const;
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private:
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uint32_t cluster_id_;
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std::vector<Core::Ptr> cores_;
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std::vector<CoreMask> barriers_;
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CacheSim::Ptr l2cache_;
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CacheCluster::Ptr icaches_;
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CacheCluster::Ptr dcaches_;
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std::vector<SharedMem::Ptr> sharedmems_;
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CacheCluster::Ptr tcaches_;
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CacheCluster::Ptr ocaches_;
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CacheCluster::Ptr rcaches_;
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ProcessorImpl* processor_;
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};
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} // namespace vortex
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