131 lines
3.9 KiB
Verilog
131 lines
3.9 KiB
Verilog
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`include "VX_define.v"
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module Vortex(
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input wire clk,
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input wire reset,
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input wire[31:0] icache_response_instruction,
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output wire[31:0] icache_request_pc_address,
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input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
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output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
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output wire[2:0] out_cache_driver_in_mem_read,
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output wire[2:0] out_cache_driver_in_mem_write,
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output wire out_cache_driver_in_valid[`NT_M1:0],
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output wire[31:0] out_cache_driver_in_data[`NT_M1:0],
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output wire out_ebreak
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);
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// Dcache Interface
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VX_dcache_response_inter VX_dcache_rsp();
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VX_dcache_request_inter VX_dcache_req();
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assign out_cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
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assign out_cache_driver_in_mem_read = VX_dcache_req.out_cache_driver_in_mem_read;
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assign out_cache_driver_in_mem_write = VX_dcache_req.out_cache_driver_in_mem_write;
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assign out_cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid;
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assign out_cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
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assign VX_dcache_rsp.in_cache_driver_out_data = in_cache_driver_out_data;
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// Icache Interface
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VX_icache_response_inter icache_response_fe();
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VX_icache_request_inter icache_request_fe();
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assign icache_response_fe.instruction = icache_response_instruction;
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assign icache_request_pc_address = icache_request_fe.pc_address;
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/////////////////////////////////////////////////////////////////////////
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// Front-end to Back-end
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VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
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wire fetch_delay;
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// Back-end to Front-end
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VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
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VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
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VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
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wire execute_branch_stall;
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wire memory_delay;
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// CSR Buses
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VX_csr_write_request_inter VX_csr_w_req();
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wire[31:0] csr_decode_csr_data;
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wire[11:0] decode_csr_address;
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VX_warp_ctl_inter VX_warp_ctl();
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wire out_gpr_stall;
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wire schedule_delay;
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VX_front_end vx_front_end(
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.clk (clk),
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.reset (reset),
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.VX_warp_ctl (VX_warp_ctl),
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.execute_branch_stall(execute_branch_stall),
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.VX_bckE_req (VX_bckE_req),
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.decode_csr_address (decode_csr_address),
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.memory_delay (memory_delay),
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.fetch_delay (fetch_delay),
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.schedule_delay (schedule_delay),
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.icache_response_fe (icache_response_fe),
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.icache_request_fe (icache_request_fe),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.fetch_ebreak (out_ebreak),
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.in_gpr_stall (out_gpr_stall)
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);
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VX_scheduler schedule(
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.clk (clk),
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.VX_bckE_req (VX_bckE_req),
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.VX_writeback_inter(VX_writeback_inter),
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.schedule_delay (schedule_delay)
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);
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VX_back_end vx_back_end(
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.fetch_delay (fetch_delay),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.csr_decode_csr_data (csr_decode_csr_data),
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.execute_branch_stall(execute_branch_stall),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.VX_dcache_rsp (VX_dcache_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_csr_w_req (VX_csr_w_req),
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.VX_writeback_inter (VX_writeback_inter),
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.out_mem_delay (memory_delay),
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.out_gpr_stall (out_gpr_stall)
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);
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VX_csr_handler vx_csr_handler(
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.clk (clk),
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.in_decode_csr_address(decode_csr_address),
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.VX_csr_w_req (VX_csr_w_req),
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.in_wb_valid (VX_writeback_inter.wb_valid[0]),
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.out_decode_csr_data (csr_decode_csr_data)
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);
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endmodule // Vortex
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