160 lines
5.8 KiB
Verilog
160 lines
5.8 KiB
Verilog
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`include "VX_cache_config.v"
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module VX_cache_miss_resrv
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#(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUMBER_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUMBER_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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)
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(
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input wire clk,
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input wire reset,
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// Miss enqueue
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input wire miss_add,
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input wire[31:0] miss_add_addr,
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input wire[`WORD_SIZE_RNG] miss_add_data,
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input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid,
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input wire[4:0] miss_add_rd,
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input wire[1:0] miss_add_wb,
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input wire[`NW_M1:0] miss_add_warp_num,
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input wire[2:0] miss_add_mem_read,
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input wire[2:0] miss_add_mem_write,
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input wire[31:0] miss_add_pc,
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output wire miss_resrv_full,
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// Broadcast Fill
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input wire is_fill_st1,
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input wire[31:0] fill_addr_st1,
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// Miss dequeue
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input wire miss_resrv_pop,
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output wire miss_resrv_valid_st0,
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output wire[31:0] miss_resrv_addr_st0,
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output wire[`WORD_SIZE_RNG] miss_resrv_data_st0,
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output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0,
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output wire[4:0] miss_resrv_rd_st0,
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output wire[1:0] miss_resrv_wb_st0,
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output wire[`NW_M1:0] miss_resrv_warp_num_st0,
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output wire[2:0] miss_resrv_mem_read_st0,
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output wire[31:0] miss_resrv_pc_st0,
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output wire[2:0] miss_resrv_mem_write_st0
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);
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// Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1)
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reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0];
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reg[MRVQ_SIZE-1:0][31:0] addr_table;
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reg[MRVQ_SIZE-1:0][31:0] pc_table;
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reg[MRVQ_SIZE-1:0] valid_table;
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reg[MRVQ_SIZE-1:0] ready_table;
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reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr;
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reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr;
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reg[31:0] size;
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// assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
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assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE);
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wire enqueue_possible = !miss_resrv_full;
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wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
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reg[MRVQ_SIZE-1:0] make_ready;
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genvar curr_e;
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generate
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for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin
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assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e]
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&& addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START];
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end
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endgenerate
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wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr];
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wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
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assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
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assign miss_resrv_pc_st0 = pc_table[dequeue_index];
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assign miss_resrv_addr_st0 = addr_table[dequeue_index];
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assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index];
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wire update_ready = (|make_ready);
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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for (i = 0; i < MRVQ_SIZE; i=i+1) metadata_table[i] <= 0;
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valid_table <= 0;
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ready_table <= 0;
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addr_table <= 0;
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pc_table <= 0;
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end else begin
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if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin
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size <= size + 1;
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valid_table[enqueue_index] <= 1;
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ready_table[enqueue_index] <= 0;
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pc_table[enqueue_index] <= miss_add_pc;
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addr_table[enqueue_index] <= miss_add_addr;
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metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write};
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tail_ptr <= tail_ptr + 1;
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end
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if (update_ready) begin
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ready_table <= ready_table | make_ready;
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end
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if (miss_resrv_pop && dequeue_possible) begin
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size <= size - 1;
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valid_table[dequeue_index] <= 0;
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ready_table[dequeue_index] <= 0;
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addr_table[dequeue_index] <= 0;
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metadata_table[dequeue_index] <= 0;
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pc_table[dequeue_index] <= 0;
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head_ptr <= head_ptr + 1;
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end
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end
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end
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endmodule |