wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
53c8cddccfc079c673afa273134d87763ed966e5
vortex/hw/rtl
History
Blaise Tine 53c8cddccf LKG build - minor update
2021-08-30 10:25:52 -07:00
..
afu
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
cache
cache multi-porting fixes + optimization
2021-08-29 18:33:49 -07:00
fp_cores
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
interfaces
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
libs
GPRs optimization - disabling BRAM's read-during-write bypass block.
2021-08-28 15:34:36 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
cache bank area optimization + multi-porting fix for l2/l3 caches
2021-08-28 21:34:06 -07:00
VX_alu_unit.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_cluster.v
LKG build - minor update
2021-08-30 10:25:52 -07:00
VX_commit.v
enabling delayed tracing
2021-08-12 20:05:43 -07:00
VX_config.vh
cache multi-porting fixes + optimization
2021-08-29 18:33:49 -07:00
VX_core.v
minor update
2021-07-20 21:42:22 -07:00
VX_csr_data.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_csr_unit.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_decode.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_define.vh
LKG build - minor update
2021-08-30 10:25:52 -07:00
VX_execute.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_fetch.v
warp scheduler optimization
2021-08-07 23:45:01 -07:00
VX_fpu_unit.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_gpr_stage.v
GPRs optimization - disabling BRAM's read-during-write bypass block.
2021-08-28 15:34:36 -07:00
VX_gpu_unit.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_ibuffer.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_icache_stage.v
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
VX_instr_demux.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_ipdom_stack.v
block ram refactoring (multi-porting supporting and simulation support)
2021-08-26 08:19:44 -07:00
VX_issue.v
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
VX_lsu_unit.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_mem_arb.v
bus arbiters refactoring
2021-07-30 16:00:09 -07:00
VX_mem_unit.v
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
VX_muldiv.v
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_pipeline.v
thread mask redesign
2021-08-05 17:32:58 -07:00
VX_platform.vh
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
VX_print_instr.vh
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_scope.vh
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_scoreboard.v
enabling delayed tracing
2021-08-12 20:05:43 -07:00
VX_smem_arb.v
bus arbiters refactoring
2021-07-30 16:00:09 -07:00
VX_types.vh
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
VX_warp_sched.v
using lzc instead of priority_encoder
2021-08-26 07:29:47 -07:00
VX_writeback.v
unused variables refactoring
2021-08-05 01:46:26 -07:00