128 lines
3.9 KiB
Verilog
128 lines
3.9 KiB
Verilog
`include "VX_define.vh"
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module VX_execute #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_BE_IO
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input wire clk,
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input wire reset,
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// CSR io interface
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VX_csr_io_req_if csr_io_req_if,
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VX_csr_io_rsp_if csr_io_rsp_if,
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// Dcache interface
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VX_cache_core_req_if dcache_req_if,
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VX_cache_core_rsp_if dcache_rsp_if,
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// perf
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VX_perf_cntrs_if perf_cntrs_if,
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// inputs
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VX_alu_req_if alu_req_if,
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VX_branch_req_if branch_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_gpu_req_if gpu_req_if,
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// outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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VX_commit_if alu_commit_if,
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VX_commit_if branch_commit_if,
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VX_commit_if lsu_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if mul_commit_if,
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VX_commit_if gpu_commit_if,
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output wire ebreak
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);
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VX_alu_unit #(
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.CORE_ID(CORE_ID)
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) alu_unit (
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.clk (clk),
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.reset (reset),
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.alu_req_if (alu_req_if),
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.alu_commit_if (alu_commit_if)
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);
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VX_branch_unit #(
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.CORE_ID(CORE_ID)
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) branch_unit (
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.clk (clk),
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.reset (reset),
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.branch_req_if (branch_req_if),
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.branch_ctl_if (branch_ctl_if),
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.branch_commit_if(branch_commit_if)
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);
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VX_lsu_unit #(
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.CORE_ID(CORE_ID)
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) lsu_unit (
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`SCOPE_SIGNALS_LSU_BIND
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.clk (clk),
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.reset (reset),
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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.lsu_req_if (lsu_req_if),
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.lsu_commit_if (lsu_commit_if)
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);
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VX_csr_pipe #(
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.CORE_ID(CORE_ID)
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) csr_pipe (
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.clk (clk),
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.reset (reset),
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.perf_cntrs_if (perf_cntrs_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.csr_req_if (csr_req_if),
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.csr_commit_if (csr_commit_if)
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);
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VX_mul_unit #(
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.CORE_ID(CORE_ID)
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) mul_unit (
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.clk (clk),
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.reset (reset),
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.mul_req_if (mul_req_if),
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.mul_commit_if (mul_commit_if)
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);
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VX_gpu_unit #(
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.CORE_ID(CORE_ID)
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) gpu_unit (
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.gpu_req_if (gpu_req_if),
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.warp_ctl_if (warp_ctl_if),
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.gpu_commit_if (gpu_commit_if)
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);
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assign ebreak = (| branch_req_if.valid) && (branch_req_if.br_op == `BR_EBREAK || branch_req_if.br_op == `BR_ECALL);
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`SCOPE_ASSIGN(scope_decode_valid, decode_if.valid);
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`SCOPE_ASSIGN(scope_decode_warp_num, decode_if.warp_num);
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`SCOPE_ASSIGN(scope_decode_curr_PC, decode_if.curr_PC);
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`SCOPE_ASSIGN(scope_decode_is_jal, decode_if.is_jal);
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`SCOPE_ASSIGN(scope_decode_rs1, decode_if.rs1);
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`SCOPE_ASSIGN(scope_decode_rs2, decode_if.rs2);
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`SCOPE_ASSIGN(scope_execute_valid, alu_req_if.valid);
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`SCOPE_ASSIGN(scope_execute_warp_num, alu_req_if.warp_num);
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`SCOPE_ASSIGN(scope_execute_curr_PC, alu_req_if.curr_PC);
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`SCOPE_ASSIGN(scope_execute_rd, alu_req_if.rd);
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`SCOPE_ASSIGN(scope_execute_a, alu_req_if.rs1_data);
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`SCOPE_ASSIGN(scope_execute_b, alu_req_if.rs2_data);
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`SCOPE_ASSIGN(scope_writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN(scope_writeback_warp_num, writeback_if.warp_num);
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`SCOPE_ASSIGN(scope_writeback_curr_PC, writeback_if.curr_PC);
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`SCOPE_ASSIGN(scope_writeback_wb, writeback_if.wb);
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`SCOPE_ASSIGN(scope_writeback_rd, writeback_if.rd);
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`SCOPE_ASSIGN(scope_writeback_data, writeback_if.data);
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endmodule
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