579 lines
15 KiB
C++
579 lines
15 KiB
C++
#include "simulator.h"
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#include <verilated.h>
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#ifdef AXI_BUS
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#include "VVortex_axi.h"
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#include "VVortex_axi__Syms.h"
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#else
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#include "VVortex.h"
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#include "VVortex__Syms.h"
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#endif
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#ifdef VCD_OUTPUT
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#include <verilated_vcd_c.h>
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#endif
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#include <mem.h>
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#define ENABLE_MEM_STALLS
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#ifndef TRACE_START_TIME
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#define TRACE_START_TIME 0ull
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#endif
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#ifndef TRACE_STOP_TIME
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#define TRACE_STOP_TIME -1ull
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#endif
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#ifndef MEM_LATENCY
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#define MEM_LATENCY 24
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#endif
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#ifndef MEM_RQ_SIZE
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#define MEM_RQ_SIZE 16
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#endif
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#ifndef MEM_STALLS_MODULO
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#define MEM_STALLS_MODULO 16
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#endif
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#ifndef VERILATOR_RESET_VALUE
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#define VERILATOR_RESET_VALUE 2
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#endif
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#define VL_WDATA_GETW(lwp, i, n, w) \
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VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w)
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using namespace vortex;
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static uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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///////////////////////////////////////////////////////////////////////////////
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static bool trace_enabled = false;
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static uint64_t trace_start_time = TRACE_START_TIME;
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static uint64_t trace_stop_time = TRACE_STOP_TIME;
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bool sim_trace_enabled() {
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if (timestamp >= trace_start_time
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&& timestamp < trace_stop_time)
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return true;
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return trace_enabled;
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}
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void sim_trace_enable(bool enable) {
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trace_enabled = enable;
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}
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///////////////////////////////////////////////////////////////////////////////
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namespace vortex {
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class VL_OBJ {
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public:
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#ifdef AXI_BUS
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VVortex_axi *device;
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#else
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VVortex *device;
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#endif
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#ifdef VCD_OUTPUT
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VerilatedVcdC *trace;
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#endif
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VL_OBJ() {
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// force random values for unitialized signals
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Verilated::randReset(VERILATOR_RESET_VALUE);
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Verilated::randSeed(50);
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// Turn off assertion before reset
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Verilated::assertOn(false);
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#ifdef AXI_BUS
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this->device = new VVortex_axi();
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#else
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this->device = new VVortex();
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#endif
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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this->trace = new VerilatedVcdC();
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this->device->trace(this->trace, 99);
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this->trace->open("trace.vcd");
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#endif
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}
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~VL_OBJ() {
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#ifdef VCD_OUTPUT
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this->trace->close();
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delete this->trace;
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#endif
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delete this->device;
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}
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};
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}
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///////////////////////////////////////////////////////////////////////////////
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Simulator::Simulator() {
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vl_obj_ = new VL_OBJ();
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ram_ = nullptr;
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// reset the device
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this->reset();
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}
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Simulator::~Simulator() {
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for (auto& buf : print_bufs_) {
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auto str = buf.second.str();
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if (!str.empty()) {
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std::cout << "#" << buf.first << ": " << str << std::endl;
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}
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}
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delete vl_obj_;
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}
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void Simulator::attach_ram(RAM* ram) {
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ram_ = ram;
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for (int b = 0; b < MEMORY_BANKS; ++b) {
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mem_rsp_vec_[b].clear();
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}
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last_mem_rsp_bank_ = 0;
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}
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void Simulator::reset() {
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print_bufs_.clear();
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for (int b = 0; b < MEMORY_BANKS; ++b) {
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mem_rsp_vec_[b].clear();
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}
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last_mem_rsp_bank_ = 0;
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mem_rd_rsp_active_ = false;
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mem_wr_rsp_active_ = false;
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#ifdef AXI_BUS
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this->reset_axi_bus();
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#else
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this->reset_mem_bus();
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#endif
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vl_obj_->device->reset = 1;
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for (int i = 0; i < RESET_DELAY; ++i) {
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vl_obj_->device->clk = 0;
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this->eval();
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vl_obj_->device->clk = 1;
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this->eval();
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}
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vl_obj_->device->reset = 0;
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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void Simulator::step() {
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vl_obj_->device->clk = 0;
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this->eval();
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#ifdef AXI_BUS
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this->eval_axi_bus(0);
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#else
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this->eval_mem_bus(0);
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#endif
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vl_obj_->device->clk = 1;
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this->eval();
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#ifdef AXI_BUS
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this->eval_axi_bus(1);
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#else
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this->eval_mem_bus(1);
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#endif
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#ifndef NDEBUG
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fflush(stdout);
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#endif
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}
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void Simulator::eval() {
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vl_obj_->device->eval();
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#ifdef VCD_OUTPUT
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if (sim_trace_enabled()) {
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vl_obj_->trace->dump(timestamp);
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}
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#endif
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++timestamp;
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}
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#ifdef AXI_BUS
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void Simulator::reset_axi_bus() {
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vl_obj_->device->m_axi_wready = 0;
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vl_obj_->device->m_axi_awready = 0;
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vl_obj_->device->m_axi_arready = 0;
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vl_obj_->device->m_axi_rvalid = 0;
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vl_obj_->device->m_axi_bvalid = 0;
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}
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void Simulator::eval_axi_bus(bool clk) {
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if (!clk) {
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mem_rd_rsp_ready_ = vl_obj_->device->m_axi_rready;
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mem_wr_rsp_ready_ = vl_obj_->device->m_axi_bready;
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return;
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}
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if (ram_ == nullptr) {
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vl_obj_->device->m_axi_wready = 0;
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vl_obj_->device->m_axi_awready = 0;
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vl_obj_->device->m_axi_arready = 0;
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return;
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}
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// update memory responses schedule
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for (int b = 0; b < MEMORY_BANKS; ++b) {
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for (auto& rsp : mem_rsp_vec_[b]) {
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if (rsp.cycles_left > 0)
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rsp.cycles_left -= 1;
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}
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}
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bool has_rd_response = false;
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bool has_wr_response = false;
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// schedule memory responses that are ready
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for (int i = 0; i < MEMORY_BANKS; ++i) {
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uint32_t b = (i + last_mem_rsp_bank_ + 1) % MEMORY_BANKS;
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if (!mem_rsp_vec_[b].empty()) {
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auto mem_rsp_it = mem_rsp_vec_[b].begin();
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if (mem_rsp_it->cycles_left <= 0) {
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has_rd_response = !mem_rsp_it->write;
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has_wr_response = mem_rsp_it->write;
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last_mem_rsp_bank_ = b;
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break;
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}
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}
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}
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// send memory read response
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if (mem_rd_rsp_active_
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&& vl_obj_->device->m_axi_rvalid && mem_rd_rsp_ready_) {
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mem_rd_rsp_active_ = false;
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}
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if (!mem_rd_rsp_active_) {
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if (has_rd_response) {
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auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin();
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/*
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printf("%0ld: [sim] MEM Rd Rsp: bank=%d, addr=%0lx, data=", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr);
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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printf("%02x", mem_rsp_it->block[(MEM_BLOCK_SIZE-1)-i]);
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}
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printf("\n");
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*/
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vl_obj_->device->m_axi_rvalid = 1;
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vl_obj_->device->m_axi_rid = mem_rsp_it->tag;
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vl_obj_->device->m_axi_rresp = 0;
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vl_obj_->device->m_axi_rlast = 1;
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memcpy((uint8_t*)vl_obj_->device->m_axi_rdata, mem_rsp_it->block.data(), MEM_BLOCK_SIZE);
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mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it);
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mem_rd_rsp_active_ = true;
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} else {
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vl_obj_->device->m_axi_rvalid = 0;
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}
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}
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// send memory write response
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if (mem_wr_rsp_active_
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&& vl_obj_->device->m_axi_bvalid && mem_wr_rsp_ready_) {
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mem_wr_rsp_active_ = false;
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}
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if (!mem_wr_rsp_active_) {
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if (has_wr_response) {
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auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin();
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/*
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printf("%0ld: [sim] MEM Wr Rsp: bank=%d, addr=%0lx\n", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr);
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*/
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vl_obj_->device->m_axi_bvalid = 1;
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vl_obj_->device->m_axi_bid = mem_rsp_it->tag;
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vl_obj_->device->m_axi_bresp = 0;
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mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it);
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mem_wr_rsp_active_ = true;
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} else {
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vl_obj_->device->m_axi_bvalid = 0;
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}
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}
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// select the memory bank
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uint32_t req_addr = vl_obj_->device->m_axi_wvalid ? vl_obj_->device->m_axi_awaddr : vl_obj_->device->m_axi_araddr;
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uint32_t req_bank = (MEMORY_BANKS >= 2) ? ((req_addr / MEM_BLOCK_SIZE) % MEMORY_BANKS) : 0;
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// handle memory stalls
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bool mem_stalled = false;
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#ifdef ENABLE_MEM_STALLS
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if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
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mem_stalled = true;
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} else
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if (mem_rsp_vec_[req_bank].size() >= MEM_RQ_SIZE) {
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mem_stalled = true;
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}
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#endif
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// process memory requests
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if (!mem_stalled) {
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if (vl_obj_->device->m_axi_wvalid || vl_obj_->device->m_axi_arvalid) {
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if (vl_obj_->device->m_axi_wvalid) {
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uint64_t byteen = vl_obj_->device->m_axi_wstrb;
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unsigned base_addr = vl_obj_->device->m_axi_awaddr;
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uint8_t* data = (uint8_t*)(vl_obj_->device->m_axi_wdata);
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// detect stdout write
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if (base_addr >= IO_COUT_ADDR
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&& base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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auto& ss_buf = print_bufs_[i];
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char c = data[i];
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ss_buf << c;
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if (c == '\n') {
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std::cout << std::dec << "#" << i << ": " << ss_buf.str() << std::flush;
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ss_buf.str("");
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}
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}
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}
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} else {
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/*
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printf("%0ld: [sim] MEM Wr: addr=%0x, byteen=%0lx, data=", timestamp, base_addr, byteen);
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]);
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}
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printf("\n");
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*/
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
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}
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}
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mem_req_t mem_req;
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mem_req.tag = vl_obj_->device->m_axi_arid;
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mem_req.addr = vl_obj_->device->m_axi_araddr;
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mem_req.cycles_left = 0;
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mem_req.write = 1;
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mem_rsp_vec_[req_bank].emplace_back(mem_req);
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}
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} else {
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mem_req_t mem_req;
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mem_req.tag = vl_obj_->device->m_axi_arid;
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mem_req.addr = vl_obj_->device->m_axi_araddr;
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ram_->read(mem_req.block.data(), vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE);
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mem_req.cycles_left = MEM_LATENCY;
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mem_req.write = 0;
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for (auto& rsp : mem_rsp_vec_[req_bank]) {
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if (mem_req.addr == rsp.addr) {
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// duplicate requests receive the same cycle delay
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mem_req.cycles_left = rsp.cycles_left;
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break;
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}
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}
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mem_rsp_vec_[req_bank].emplace_back(mem_req);
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}
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}
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}
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vl_obj_->device->m_axi_wready = !mem_stalled;
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vl_obj_->device->m_axi_awready = !mem_stalled;
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vl_obj_->device->m_axi_arready = !mem_stalled;
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}
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#else
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void Simulator::reset_mem_bus() {
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vl_obj_->device->mem_req_ready = 0;
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vl_obj_->device->mem_rsp_valid = 0;
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}
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void Simulator::eval_mem_bus(bool clk) {
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if (!clk) {
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mem_rd_rsp_ready_ = vl_obj_->device->mem_rsp_ready;
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return;
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}
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if (ram_ == nullptr) {
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vl_obj_->device->mem_req_ready = 0;
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return;
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}
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// update memory responses schedule
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for (int b = 0; b < MEMORY_BANKS; ++b) {
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for (auto& rsp : mem_rsp_vec_[b]) {
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if (rsp.cycles_left > 0)
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rsp.cycles_left -= 1;
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}
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}
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bool has_response = false;
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// schedule memory responses that are ready
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for (int i = 0; i < MEMORY_BANKS; ++i) {
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uint32_t b = (i + last_mem_rsp_bank_ + 1) % MEMORY_BANKS;
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if (!mem_rsp_vec_[b].empty()
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&& (mem_rsp_vec_[b].begin()->cycles_left) <= 0) {
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has_response = true;
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last_mem_rsp_bank_ = b;
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break;
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}
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}
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// send memory response
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if (mem_rd_rsp_active_
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&& vl_obj_->device->mem_rsp_valid && mem_rd_rsp_ready_) {
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mem_rd_rsp_active_ = false;
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}
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if (!mem_rd_rsp_active_) {
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if (has_response) {
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vl_obj_->device->mem_rsp_valid = 1;
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auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin();
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/*
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printf("%0ld: [sim] MEM Rd: bank=%d, addr=%0lx, data=", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr);
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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printf("%02x", mem_rsp_it->block[(MEM_BLOCK_SIZE-1)-i]);
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}
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printf("\n");
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*/
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memcpy((uint8_t*)vl_obj_->device->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE);
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vl_obj_->device->mem_rsp_tag = mem_rsp_it->tag;
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mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it);
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mem_rd_rsp_active_ = true;
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} else {
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vl_obj_->device->mem_rsp_valid = 0;
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}
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}
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// select the memory bank
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uint32_t req_bank = (MEMORY_BANKS >= 2) ? (vl_obj_->device->mem_req_addr % MEMORY_BANKS) : 0;
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// handle memory stalls
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bool mem_stalled = false;
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#ifdef ENABLE_MEM_STALLS
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if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
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mem_stalled = true;
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} else
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if (mem_rsp_vec_[req_bank].size() >= MEM_RQ_SIZE) {
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mem_stalled = true;
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}
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#endif
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// process memory requests
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if (!mem_stalled) {
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if (vl_obj_->device->mem_req_valid) {
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if (vl_obj_->device->mem_req_rw) {
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uint64_t byteen = vl_obj_->device->mem_req_byteen;
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unsigned base_addr = (vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE);
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uint8_t* data = (uint8_t*)(vl_obj_->device->mem_req_data);
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if (base_addr >= IO_COUT_ADDR
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&& base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
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for (int i = 0; i < IO_COUT_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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auto& ss_buf = print_bufs_[i];
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char c = data[i];
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ss_buf << c;
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if (c == '\n') {
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std::cout << std::dec << "#" << i << ": " << ss_buf.str() << std::flush;
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ss_buf.str("");
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}
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}
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}
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} else {
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/*
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printf("%0ld: [sim] MEM Wr: addr=%0x, byteen=%0lx, data=", timestamp, base_addr, byteen);
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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printf("%02x", data[(MEM_BLOCK_SIZE-1)-i]);
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}
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printf("\n");
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*/
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
mem_req_t mem_req;
|
|
mem_req.tag = vl_obj_->device->mem_req_tag;
|
|
mem_req.addr = (vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE);
|
|
ram_->read(mem_req.block.data(), vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE);
|
|
mem_req.cycles_left = MEM_LATENCY;
|
|
for (auto& rsp : mem_rsp_vec_[req_bank]) {
|
|
if (mem_req.addr == rsp.addr) {
|
|
// duplicate requests receive the same cycle delay
|
|
mem_req.cycles_left = rsp.cycles_left;
|
|
break;
|
|
}
|
|
}
|
|
mem_rsp_vec_[req_bank].emplace_back(mem_req);
|
|
}
|
|
}
|
|
}
|
|
|
|
vl_obj_->device->mem_req_ready = !mem_stalled;
|
|
}
|
|
|
|
#endif
|
|
|
|
void Simulator::wait(uint32_t cycles) {
|
|
for (int i = 0; i < cycles; ++i) {
|
|
this->step();
|
|
}
|
|
}
|
|
|
|
bool Simulator::is_busy() const {
|
|
return vl_obj_->device->busy;
|
|
}
|
|
|
|
int Simulator::run() {
|
|
int exitcode = 0;
|
|
|
|
#ifndef NDEBUG
|
|
std::cout << std::dec << timestamp << ": [sim] run()" << std::endl;
|
|
#endif
|
|
|
|
// execute program
|
|
while (vl_obj_->device->busy) {
|
|
if (get_ebreak()) {
|
|
exitcode = get_last_wb_value(3);
|
|
break;
|
|
}
|
|
this->step();
|
|
}
|
|
|
|
// wait 5 cycles to flush the pipeline
|
|
this->wait(5);
|
|
|
|
return exitcode;
|
|
}
|
|
|
|
bool Simulator::get_ebreak() const {
|
|
#ifdef AXI_BUS
|
|
return (int)vl_obj_->device->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak;
|
|
#else
|
|
return (int)vl_obj_->device->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak;
|
|
#endif
|
|
}
|
|
|
|
int Simulator::get_last_wb_value(int reg) const {
|
|
#ifdef AXI_BUS
|
|
return (int)vl_obj_->device->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
|
|
#else
|
|
return (int)vl_obj_->device->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
|
|
#endif
|
|
}
|
|
|
|
void Simulator::print_stats(std::ostream& out) {
|
|
out << std::left;
|
|
out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl;
|
|
} |