70 lines
1.8 KiB
Verilog
70 lines
1.8 KiB
Verilog
`include "VX_platform.vh"
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module VX_ipdom_stack #(
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parameter WIDTH = 1,
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parameter DEPTH = 1
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) (
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input wire clk,
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input wire reset,
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input wire [WIDTH - 1:0] q1,
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input wire [WIDTH - 1:0] q2,
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output wire [WIDTH - 1:0] d,
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input wire push,
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input wire pop,
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output wire empty,
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output wire full
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);
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localparam STACK_SIZE = 2 ** DEPTH;
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`NO_RW_RAM_CHECK reg [WIDTH-1:0] stack_1 [0:STACK_SIZE-1];
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`NO_RW_RAM_CHECK reg [WIDTH-1:0] stack_2 [0:STACK_SIZE-1];
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reg is_part [0:STACK_SIZE-1];
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reg [DEPTH-1:0] rd_ptr, wr_ptr;
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reg [WIDTH - 1:0] d1, d2;
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reg p;
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr <= 0;
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wr_ptr <= 0;
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end else begin
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if (push) begin
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rd_ptr <= wr_ptr;
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wr_ptr <= wr_ptr + DEPTH'(1);
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end else if (pop) begin
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wr_ptr <= wr_ptr - DEPTH'(is_part[rd_ptr]);
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rd_ptr <= rd_ptr - DEPTH'(is_part[rd_ptr]);
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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stack_1[wr_ptr] <= q1;
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end
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end
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assign d1 = stack_1[rd_ptr];
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always @(posedge clk) begin
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if (push) begin
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stack_2[wr_ptr] <= q2;
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end
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end
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assign d2 = stack_2[rd_ptr];
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always @(posedge clk) begin
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if (push) begin
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is_part[wr_ptr] <= 0;
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end else if (pop) begin
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is_part[rd_ptr] <= 1;
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end
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end
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assign p = is_part[rd_ptr];
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assign d = p ? d1 : d2;
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assign empty = ~(| wr_ptr);
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assign full = ((STACK_SIZE-1) == wr_ptr);
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endmodule |