159 lines
6.8 KiB
Verilog
159 lines
6.8 KiB
Verilog
`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_issue
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_writeback_if writeback_if,
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VX_csr_to_issue_if csr_to_issue_if,
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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VX_decode_if ibuf_deq_if();
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VX_decode_if execute_if();
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VX_gpr_req_if gpr_req_if();
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VX_gpr_rsp_if gpr_rsp_if();
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wire scoreboard_delay;
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wire [`NW_BITS-1:0] deq_wid_next;
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VX_ibuffer #(
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.CORE_ID(CORE_ID)
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) ibuffer (
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.clk (clk),
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.reset (reset),
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.freeze (~gpr_req_if.ready),
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.ibuf_enq_if (decode_if),
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.deq_wid_next (deq_wid_next),
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.ibuf_deq_if (ibuf_deq_if)
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);
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VX_scoreboard #(
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.CORE_ID(CORE_ID)
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) scoreboard (
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.clk (clk),
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.reset (reset),
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.ibuf_deq_if (ibuf_deq_if),
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.writeback_if (writeback_if),
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.deq_wid_next (deq_wid_next),
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.exe_delay (~execute_if.ready),
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.gpr_delay (~gpr_req_if.ready),
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.delay (scoreboard_delay)
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);
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assign gpr_req_if.valid = ibuf_deq_if.valid && ~scoreboard_delay;
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assign gpr_req_if.wid = ibuf_deq_if.wid;
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assign gpr_req_if.PC = ibuf_deq_if.PC;
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assign gpr_req_if.rs1 = ibuf_deq_if.rs1;
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assign gpr_req_if.rs2 = ibuf_deq_if.rs2;
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assign gpr_req_if.rs3 = ibuf_deq_if.rs3;
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assign gpr_req_if.use_rs3 = ibuf_deq_if.use_rs3;
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assign gpr_rsp_if.ready = execute_if.ready;
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (reset),
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.writeback_if (writeback_if),
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.gpr_req_if (gpr_req_if),
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.gpr_rsp_if (gpr_rsp_if)
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);
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`UNUSED_VAR (gpr_rsp_if.valid);
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assign execute_if.valid = ibuf_deq_if.valid && gpr_req_if.ready && ~scoreboard_delay;
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assign execute_if.wid = ibuf_deq_if.wid;
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assign execute_if.tmask = ibuf_deq_if.tmask;
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assign execute_if.PC = ibuf_deq_if.PC;
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assign execute_if.ex_type = ibuf_deq_if.ex_type;
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assign execute_if.op_type = ibuf_deq_if.op_type;
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assign execute_if.op_mod = ibuf_deq_if.op_mod;
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assign execute_if.wb = ibuf_deq_if.wb;
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assign execute_if.rd = ibuf_deq_if.rd;
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assign execute_if.rs1 = ibuf_deq_if.rs1;
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assign execute_if.imm = ibuf_deq_if.imm;
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assign execute_if.rs1_is_PC = ibuf_deq_if.rs1_is_PC;
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assign execute_if.rs2_is_imm = ibuf_deq_if.rs2_is_imm;
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VX_instr_demux instr_demux (
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.clk (clk),
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.reset (reset),
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.execute_if (execute_if),
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.gpr_rsp_if (gpr_rsp_if),
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.csr_to_issue_if(csr_to_issue_if),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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.mul_req_if (mul_req_if),
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.fpu_req_if (fpu_req_if),
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.gpu_req_if (gpu_req_if)
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);
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`SCOPE_ASSIGN (issue_fire, ibuf_deq_if.valid && ibuf_deq_if.ready);
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`SCOPE_ASSIGN (issue_wid, ibuf_deq_if.wid);
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`SCOPE_ASSIGN (issue_tmask, ibuf_deq_if.tmask);
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`SCOPE_ASSIGN (issue_pc, ibuf_deq_if.PC);
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`SCOPE_ASSIGN (issue_ex_type, ibuf_deq_if.ex_type);
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`SCOPE_ASSIGN (issue_op_type, ibuf_deq_if.op_type);
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`SCOPE_ASSIGN (issue_op_mod, ibuf_deq_if.op_mod);
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`SCOPE_ASSIGN (issue_wb, ibuf_deq_if.wb);
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`SCOPE_ASSIGN (issue_rd, ibuf_deq_if.rd);
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`SCOPE_ASSIGN (issue_rs1, ibuf_deq_if.rs1);
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`SCOPE_ASSIGN (issue_rs2, ibuf_deq_if.rs2);
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`SCOPE_ASSIGN (issue_rs3, ibuf_deq_if.rs3);
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`SCOPE_ASSIGN (issue_imm, ibuf_deq_if.imm);
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`SCOPE_ASSIGN (issue_rs1_is_pc, ibuf_deq_if.rs1_is_PC);
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`SCOPE_ASSIGN (issue_rs2_is_imm, ibuf_deq_if.rs2_is_imm);
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`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
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`SCOPE_ASSIGN (gpr_delay, ~gpr_req_if.ready);
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`SCOPE_ASSIGN (execute_delay, ~execute_if.ready);
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`SCOPE_ASSIGN (gpr_rsp_valid, gpr_rsp_if.valid);
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`SCOPE_ASSIGN (gpr_rsp_wid, gpr_rsp_if.wid);
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`SCOPE_ASSIGN (gpr_rsp_pc, gpr_rsp_if.PC);
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`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
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`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data);
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`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data);
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`SCOPE_ASSIGN (writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN (writeback_wid, writeback_if.wid);
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`SCOPE_ASSIGN (writeback_pc, writeback_if.PC);
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`SCOPE_ASSIGN (writeback_rd, writeback_if.rd);
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`SCOPE_ASSIGN (writeback_data, writeback_if.data);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_req_if.valid && alu_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, alu_req_if.wid, alu_req_if.PC, alu_req_if.tmask, alu_req_if.rs1_data, alu_req_if.rs2_data);
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end
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if (lsu_req_if.valid && lsu_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=LSU, tmask=%b, rw=%b, byteen=%b, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, lsu_req_if.tmask, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
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end
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if (csr_req_if.valid && csr_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=CSR, tmask=%b, addr=%0h, mask=%0h", $time, CORE_ID, csr_req_if.wid, csr_req_if.PC, csr_req_if.tmask, csr_req_if.csr_addr, csr_req_if.csr_mask);
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end
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if (mul_req_if.valid && mul_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=MUL, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, mul_req_if.wid, mul_req_if.PC, mul_req_if.tmask, mul_req_if.rs1_data, mul_req_if.rs2_data);
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end
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if (fpu_req_if.valid && fpu_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rs1_data=%0h, rs2_data=%0h, rs3_data=%0h", $time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data);
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end
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if (gpu_req_if.valid && gpu_req_if.ready) begin
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$display("%t: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, gpu_req_if.wid, gpu_req_if.PC, gpu_req_if.tmask, gpu_req_if.rs1_data, gpu_req_if.rs2_data);
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end
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end
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`endif
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endmodule |