101 lines
4.0 KiB
Verilog
101 lines
4.0 KiB
Verilog
`include "VX_define.vh"
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module VX_mem_arb #(
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parameter NUM_REQUESTS = 1,
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parameter WORD_SIZE = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1,
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parameter WORD_WIDTH = WORD_SIZE * 8,
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parameter ADDR_WIDTH = 32 - `CLOG2(WORD_SIZE),
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parameter REQS_BITS = `CLOG2(NUM_REQUESTS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQUESTS-1:0] mem_req_valid_in,
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input wire [NUM_REQUESTS-1:0] mem_req_rw_in,
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input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] mem_req_byteen_in,
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input wire [NUM_REQUESTS-1:0][ADDR_WIDTH-1:0] mem_req_addr_in,
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input wire [NUM_REQUESTS-1:0][WORD_WIDTH-1:0] mem_req_data_in,
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input wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] mem_req_tag_in,
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output wire [NUM_REQUESTS-1:0] mem_req_ready_in,
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// input response
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output wire [NUM_REQUESTS-1:0] mem_rsp_valid_in,
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output wire [NUM_REQUESTS-1:0][WORD_WIDTH-1:0] mem_rsp_data_in,
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output wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] mem_rsp_tag_in,
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input wire [NUM_REQUESTS-1:0] mem_rsp_ready_in,
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// output request
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output wire mem_req_valid_out,
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output wire mem_req_rw_out,
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output wire [WORD_SIZE-1:0] mem_req_byteen_out,
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output wire [ADDR_WIDTH-1:0] mem_req_addr_out,
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output wire [WORD_WIDTH-1:0] mem_req_data_out,
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output wire [TAG_OUT_WIDTH-1:0] mem_req_tag_out,
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input wire mem_req_ready_out,
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// output response
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input wire mem_rsp_valid_out,
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input wire [WORD_WIDTH-1:0] mem_rsp_data_out,
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input wire [TAG_OUT_WIDTH-1:0] mem_rsp_tag_out,
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output wire mem_rsp_ready_out
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);
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if (NUM_REQUESTS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign mem_req_valid_out = mem_req_valid_in;
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assign mem_req_rw_out = mem_req_rw_in;
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assign mem_req_byteen_out = mem_req_byteen_in;
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assign mem_req_addr_out = mem_req_addr_in;
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assign mem_req_data_out = mem_req_data_in;
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assign mem_req_tag_out = mem_req_tag_in;
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assign mem_req_ready_in = mem_req_ready_out;
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assign mem_rsp_valid_in = mem_rsp_valid_out;
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assign mem_rsp_data_in = mem_rsp_data_out;
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assign mem_rsp_tag_in = mem_rsp_tag_out;
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assign mem_rsp_ready_out = mem_rsp_ready_in;
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end else begin
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reg [REQS_BITS-1:0] bus_req_sel;
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VX_rr_arbiter #(
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.N(NUM_REQUESTS)
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) arbiter (
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.clk (clk),
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.reset (reset),
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.requests (mem_req_valid_in),
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.grant_index (bus_req_sel),
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`UNUSED_PIN (grant_valid),
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`UNUSED_PIN (grant_onehot)
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);
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assign mem_req_valid_out = mem_req_valid_in [bus_req_sel];
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assign mem_req_rw_out = mem_req_rw_in [bus_req_sel];
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assign mem_req_byteen_out = mem_req_byteen_in [bus_req_sel];
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assign mem_req_addr_out = mem_req_addr_in [bus_req_sel];
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assign mem_req_data_out = mem_req_data_in [bus_req_sel];
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assign mem_req_tag_out = {mem_req_tag_in [bus_req_sel], REQS_BITS'(bus_req_sel)};
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign mem_req_ready_in[i] = mem_req_ready_out && (bus_req_sel == REQS_BITS'(i));
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end
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wire [REQS_BITS-1:0] bus_rsp_sel = mem_rsp_tag_out[REQS_BITS-1:0];
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign mem_rsp_valid_in[i] = mem_rsp_valid_out && (bus_rsp_sel == REQS_BITS'(i));
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assign mem_rsp_data_in[i] = mem_rsp_data_out;
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assign mem_rsp_tag_in[i] = mem_rsp_tag_out[REQS_BITS +: TAG_IN_WIDTH];
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end
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assign mem_rsp_ready_out = mem_rsp_ready_in[bus_rsp_sel];
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end
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endmodule |