56 lines
2.1 KiB
Verilog
56 lines
2.1 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_dram_req_arb #(
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 0,
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// Size of a word in bytes
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parameter WORD_SIZE = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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input wire [NUM_BANKS-1:0] per_bank_dram_req_valid,
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input wire [NUM_BANKS-1:0] per_bank_dram_req_rw,
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input wire [NUM_BANKS-1:0][BANK_LINE_SIZE-1:0] per_bank_dram_req_byteen,
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input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_req_addr,
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input wire [NUM_BANKS-1:0][`BANK_LINE_WIDTH-1:0] per_bank_dram_req_data,
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output wire [NUM_BANKS-1:0] per_bank_dram_req_ready,
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// Output
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output wire dram_req_valid,
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output wire dram_req_rw,
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output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
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output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
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input wire dram_req_ready
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);
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wire [`BANK_BITS-1:0] sel_bank;
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wire sel_valid;
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VX_fixed_arbiter #(
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.N(NUM_BANKS)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (per_bank_dram_req_valid),
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.grant_index (sel_bank),
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.grant_valid (sel_valid),
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`UNUSED_PIN (grant_onehot)
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);
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assign dram_req_valid = sel_valid;
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assign dram_req_rw = per_bank_dram_req_rw[sel_bank];
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assign dram_req_byteen = per_bank_dram_req_byteen[sel_bank];
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assign dram_req_addr = per_bank_dram_req_addr[sel_bank];
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assign dram_req_data = per_bank_dram_req_data[sel_bank];
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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assign per_bank_dram_req_ready[i] = dram_req_ready && (sel_bank == `BANK_BITS'(i));
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end
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endmodule
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