70 lines
1.9 KiB
Verilog
70 lines
1.9 KiB
Verilog
`include "VX_platform.vh"
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module VX_fair_arbiter #(
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parameter N = 1
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) (
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input wire clk,
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input wire reset,
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input wire [N-1:0] requests,
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output wire [`LOG2UP(N)-1:0] grant_index,
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output wire [N-1:0] grant_onehot,
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output wire grant_valid
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);
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if (N == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign grant_index = 0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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reg [N-1:0] requests_use;
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wire [N-1:0] update_value;
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wire [N-1:0] late_value;
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wire refill;
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wire [N-1:0] refill_value;
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reg [N-1:0] refill_original;
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always @(posedge clk) begin
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if (reset) begin
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requests_use <= 0;
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refill_original <= 0;
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end else begin
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if (refill) begin
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requests_use <= refill_value;
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refill_original <= refill_value;
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end else begin
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requests_use <= update_value;
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end
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end
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end
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assign refill = (requests_use == 0);
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assign refill_value = requests;
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reg [N-1:0] grant_onehot_r;
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VX_priority_encoder #(
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.N(N)
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) priority_encoder (
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.data_in (requests_use),
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.data_out (grant_index),
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.valid_out (grant_valid)
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);
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always @(*) begin
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grant_onehot_r = N'(0);
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grant_onehot_r[grant_index] = 1;
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end
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assign grant_onehot = grant_onehot_r;
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assign late_value = ((refill_original ^ requests) & ~refill_original);
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assign update_value = (requests_use & ~grant_onehot_r) | late_value;
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end
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endmodule
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