128 lines
4.3 KiB
Verilog
128 lines
4.3 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_snp_forwarder #(
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parameter BANK_LINE_SIZE = 0,
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parameter NUM_REQUESTS = 0,
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parameter SNRQ_SIZE = 0,
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parameter SNP_REQ_TAG_WIDTH = 0,
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parameter SNP_FWD_TAG_WIDTH = 0
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) (
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input wire clk,
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input wire reset,
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// Snoop request
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input wire snp_req_valid,
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input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire [`DRAM_ADDR_WIDTH-1:0] snp_rsp_addr,
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output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// Snoop Forwarding out
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output wire [NUM_REQUESTS-1:0] snp_fwdout_valid,
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output wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr,
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output wire [NUM_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdout_tag,
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input wire [NUM_REQUESTS-1:0] snp_fwdout_ready,
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// Snoop forwarding in
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input wire [NUM_REQUESTS-1:0] snp_fwdin_valid,
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input wire [NUM_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag,
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output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
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);
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reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
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reg [`REQS_BITS-1:0] fwdin_sel;
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wire [`LOG2UP(SNRQ_SIZE)-1:0] sfq_write_addr, sfq_read_addr, dbg_sfq_write_addr;
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wire sfq_push, sfq_pop, sfq_full;
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wire fwdin_valid;
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wire [SNP_FWD_TAG_WIDTH-1:0] fwdin_tag;
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wire fwdin_ready = snp_rsp_ready;
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wire fwdin_taken = fwdin_valid && fwdin_ready;
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wire fwdout_ready = (& snp_fwdout_ready);
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assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[sfq_read_addr]); // send response
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assign sfq_read_addr = fwdin_tag[`LOG2UP(SNRQ_SIZE)-1:0];
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assign sfq_push = snp_req_valid && fwdout_ready;
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assign sfq_pop = snp_rsp_valid;
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VX_indexable_queue #(
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.DATAW (`LOG2UP(SNRQ_SIZE) + `DRAM_ADDR_WIDTH+SNP_REQ_TAG_WIDTH),
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.SIZE (SNRQ_SIZE)
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) snp_fwd_queue (
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.clk (clk),
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.reset (reset),
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.write_data ({sfq_write_addr, snp_req_addr, snp_req_tag}),
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.write_addr (sfq_write_addr),
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.push (sfq_push),
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.full (sfq_full),
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.pop (sfq_pop),
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.read_addr (sfq_read_addr),
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.read_data ({dbg_sfq_write_addr, snp_rsp_addr, snp_rsp_tag})
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);
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always @(posedge clk) begin
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if (reset) begin
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//--
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end else begin
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if (sfq_push) begin
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pending_cntrs[sfq_write_addr] <= NUM_REQUESTS;
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end
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if (fwdin_taken) begin
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pending_cntrs[sfq_read_addr] <= pending_cntrs[sfq_read_addr] - 1;
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assert(sfq_read_addr == dbg_sfq_write_addr);
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end
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end
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end
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genvar i;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign snp_fwdout_valid[i] = snp_req_valid && !sfq_full;
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assign snp_fwdout_addr[i] = snp_req_addr;
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assign snp_fwdout_tag[i] = sfq_write_addr;
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end
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assign snp_req_ready = !sfq_full && fwdout_ready;
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always @(posedge clk) begin
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if (reset) begin
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fwdin_sel <= 0;
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end else begin
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fwdin_sel <= fwdin_sel + 1;
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end
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end
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assign fwdin_valid = snp_fwdin_valid[fwdin_sel];
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assign fwdin_tag = snp_fwdin_tag[fwdin_sel];
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i));
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end
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`ifdef DBG_PRINT_CACHE_SNP
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always_ff @(posedge clk) begin
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if (snp_req_valid && snp_req_ready) begin
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$display("%t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag);
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end
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if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
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$display("%t: snp fwd_out: addr=%0h, tag=%0h", $time, snp_fwdout_addr[0], snp_fwdout_tag[0]);
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end
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if (fwdin_valid && fwdin_ready) begin
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$display("%t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag);
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end
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if (snp_rsp_valid && snp_rsp_ready) begin
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$display("%t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
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end
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end
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`endif
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endmodule |