c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
251 lines
7.5 KiB
Systemverilog
251 lines
7.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_socket import VX_gpu_pkg::*; #(
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parameter SOCKET_ID = 0
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) (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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`endif
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// DCRs
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VX_dcr_bus_if.slave dcr_bus_if,
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// Memory
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VX_mem_bus_if.master mem_bus_if,
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`ifdef GBAR_ENABLE
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// Barrier
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VX_gbar_bus_if.master gbar_bus_if,
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`endif
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// simulation helper signals
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output wire sim_ebreak,
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
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// Status
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output wire busy
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);
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if per_core_gbar_bus_if[`SOCKET_SIZE]();
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`RESET_RELAY (gbar_arb_reset, reset);
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VX_gbar_arb #(
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.NUM_REQS (`SOCKET_SIZE),
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.OUT_REG ((`SOCKET_SIZE > 1) ? 2 : 0)
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) gbar_arb (
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.clk (clk),
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.reset (gbar_arb_reset),
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.bus_in_if (per_core_gbar_bus_if),
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.bus_out_if (gbar_bus_if)
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);
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`endif
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///////////////////////////////////////////////////////////////////////////
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`ifdef PERF_ENABLE
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VX_mem_perf_if mem_perf_tmp_if();
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cache_perf_t perf_icache;
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cache_perf_t perf_dcache;
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assign mem_perf_tmp_if.icache = perf_icache;
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assign mem_perf_tmp_if.dcache = perf_dcache;
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assign mem_perf_tmp_if.l2cache = mem_perf_if.l2cache;
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assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
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assign mem_perf_tmp_if.smem = 'x;
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assign mem_perf_tmp_if.mem = mem_perf_if.mem;
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`endif
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_LINE_SIZE),
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.TAG_WIDTH (ICACHE_MEM_TAG_WIDTH)
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) icache_mem_bus_if();
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_LINE_SIZE),
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.TAG_WIDTH (DCACHE_MEM_TAG_WIDTH)
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) dcache_mem_bus_if();
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_TAG_WIDTH)
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) cache_mem_bus_if[2]();
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
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) mem_bus_tmp_if[1]();
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`ASSIGN_VX_MEM_BUS_IF_X (cache_mem_bus_if[0], icache_mem_bus_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_BUS_IF_X (cache_mem_bus_if[1], dcache_mem_bus_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
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`RESET_RELAY (mem_arb_reset, reset);
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VX_mem_arb #(
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.NUM_INPUTS (2),
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_TAG_WIDTH),
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.TAG_SEL_IDX (1), // Skip 0 for NC flag
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.ARBITER ("R"),
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.OUT_REG_REQ (2),
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.OUT_REG_RSP (2)
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) mem_arb (
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.clk (clk),
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.reset (mem_arb_reset),
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.bus_in_if (cache_mem_bus_if),
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.bus_out_if (mem_bus_tmp_if)
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);
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`ASSIGN_VX_MEM_BUS_IF (mem_bus_if, mem_bus_tmp_if[0]);
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///////////////////////////////////////////////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_WORD_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH)
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) per_core_icache_bus_if[`SOCKET_SIZE]();
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`RESET_RELAY (icache_reset, reset);
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VX_cache_cluster #(
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.INSTANCE_ID ($sformatf("socket%0d-icache", SOCKET_ID)),
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.NUM_UNITS (`NUM_ICACHES),
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.NUM_INPUTS (`SOCKET_SIZE),
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.TAG_SEL_IDX (0),
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.CACHE_SIZE (`ICACHE_SIZE),
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.LINE_SIZE (ICACHE_LINE_SIZE),
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.NUM_BANKS (1),
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.NUM_WAYS (`ICACHE_NUM_WAYS),
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.WORD_SIZE (ICACHE_WORD_SIZE),
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.NUM_REQS (1),
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.CRSQ_SIZE (`ICACHE_CRSQ_SIZE),
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.MSHR_SIZE (`ICACHE_MSHR_SIZE),
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.MRSQ_SIZE (`ICACHE_MRSQ_SIZE),
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.MREQ_SIZE (`ICACHE_MREQ_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH),
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.UUID_WIDTH (`UUID_WIDTH),
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.WRITE_ENABLE (0),
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.CORE_OUT_REG (2),
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.MEM_OUT_REG (2)
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) icache (
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`ifdef PERF_ENABLE
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.cache_perf (perf_icache),
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`endif
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.clk (clk),
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.reset (icache_reset),
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.core_bus_if (per_core_icache_bus_if),
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.mem_bus_if (icache_mem_bus_if)
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);
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///////////////////////////////////////////////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
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) per_core_dcache_bus_if[`SOCKET_SIZE * DCACHE_NUM_REQS]();
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`RESET_RELAY (dcache_reset, reset);
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VX_cache_cluster #(
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.INSTANCE_ID ($sformatf("socket%0d-dcache", SOCKET_ID)),
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.NUM_UNITS (`NUM_DCACHES),
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.NUM_INPUTS (`SOCKET_SIZE),
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.TAG_SEL_IDX (1),
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.CACHE_SIZE (`DCACHE_SIZE),
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.LINE_SIZE (DCACHE_LINE_SIZE),
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.NUM_BANKS (`DCACHE_NUM_BANKS),
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.NUM_WAYS (`DCACHE_NUM_WAYS),
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.WORD_SIZE (DCACHE_WORD_SIZE),
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.NUM_REQS (DCACHE_NUM_REQS),
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.CRSQ_SIZE (`DCACHE_CRSQ_SIZE),
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.MSHR_SIZE (`DCACHE_MSHR_SIZE),
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.MRSQ_SIZE (`DCACHE_MRSQ_SIZE),
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.MREQ_SIZE (`DCACHE_MREQ_SIZE),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH),
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.UUID_WIDTH (`UUID_WIDTH),
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.WRITE_ENABLE (1),
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.NC_ENABLE (1),
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.CORE_OUT_REG (`SM_ENABLED ? 2 : 1),
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.MEM_OUT_REG (2)
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) dcache (
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`ifdef PERF_ENABLE
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.cache_perf (perf_dcache),
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`endif
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.clk (clk),
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.reset (dcache_reset),
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.core_bus_if (per_core_dcache_bus_if),
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.mem_bus_if (dcache_mem_bus_if)
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);
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///////////////////////////////////////////////////////////////////////////
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wire [`SOCKET_SIZE-1:0] per_core_sim_ebreak;
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wire [`SOCKET_SIZE-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_core_sim_wb_value;
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assign sim_ebreak = per_core_sim_ebreak[0];
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assign sim_wb_value = per_core_sim_wb_value[0];
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`UNUSED_VAR (per_core_sim_ebreak)
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`UNUSED_VAR (per_core_sim_wb_value)
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wire [`SOCKET_SIZE-1:0] per_core_busy;
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`BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, (`SOCKET_SIZE > 1));
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`SCOPE_IO_SWITCH (`SOCKET_SIZE)
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// Generate all cores
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for (genvar i = 0; i < `SOCKET_SIZE; ++i) begin
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`RESET_RELAY (core_reset, reset);
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VX_core #(
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.CORE_ID ((SOCKET_ID * `SOCKET_SIZE) + i)
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) core (
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`SCOPE_IO_BIND (i)
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.clk (clk),
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.reset (core_reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_tmp_if),
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`endif
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.dcr_bus_if (core_dcr_bus_if),
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.dcache_bus_if (per_core_dcache_bus_if[i * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]),
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.icache_bus_if (per_core_icache_bus_if[i]),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (per_core_gbar_bus_if[i]),
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`endif
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.sim_ebreak (per_core_sim_ebreak[i]),
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.sim_wb_value (per_core_sim_wb_value[i]),
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.busy (per_core_busy[i])
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);
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end
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`BUFFER_BUSY (busy, (| per_core_busy), (`SOCKET_SIZE > 1));
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endmodule
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