c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
78 lines
2.0 KiB
C++
78 lines
2.0 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifndef DEBUG_LEVEL
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#define DEBUG_LEVEL 3
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#endif
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#define DEBUG_HEADER << "DEBUG "
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//#define DEBUG_HEADER << "DEBUG " << __FILE__ << ':' << std::dec << __LINE__ << ": "
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#define TRACE_HEADER << "TRACE "
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//#define TRACE_HEADER << "DEBUG " << __FILE__ << ':' << std::dec << __LINE__ << ": "
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#ifndef NDEBUG
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#include <iostream>
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#include <iomanip>
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#define DP(lvl, x) do { \
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if ((lvl) <= DEBUG_LEVEL) { \
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std::cout DEBUG_HEADER << x << std::endl; \
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} \
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} while(0)
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#define DPH(lvl, x) do { \
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if ((lvl) <= DEBUG_LEVEL) { \
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std::cout DEBUG_HEADER << x; \
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} \
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} while(0)
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#define DPN(lvl, x) do { \
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if ((lvl) <= DEBUG_LEVEL) { \
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std::cout << x; \
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} \
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} while(0)
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#define DT(lvl, x) do { \
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if ((lvl) <= DEBUG_LEVEL) { \
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std::cout TRACE_HEADER << std::setw(10) << std::dec << SimPlatform::instance().cycles() << std::setw(0) << ": " << x << std::endl; \
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} \
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} while(0)
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#define DTH(lvl, x) do { \
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if ((lvl) <= DEBUG_LEVEL) { \
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std::cout TRACE_HEADER << std::setw(10) << std::dec << SimPlatform::instance().cycles() << std::setw(0) << ": " << x; \
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} \
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} while(0)
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#define DTN(lvl, x) do { \
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if ((lvl) <= DEBUG_LEVEL) { \
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std::cout << x; \
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} \
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} while(0)
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#else
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#define DP(lvl, x) do {} while(0)
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#define DPH(lvl, x) do {} while(0)
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#define DPN(lvl, x) do {} while(0)
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#define DT(lvl, x) do {} while(0)
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#define DTH(lvl, x) do {} while(0)
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#define DTN(lvl, x) do {} while(0)
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#endif |